Patents Represented by Law Firm Pearne, Gordon, McGoy & Granger LLP
  • Patent number: 6040706
    Abstract: Semiconductor chips 15 are separated from one another by cutting a semiconductor wafer along scribing lines, and are fitted in recesses 11 formed in a contactor 10. Bump electrodes 13 are brought into contact with the pad electrodes of the semiconductor chips, so that the former electrodes are electrically connected to the latter electrodes. Each of the recesses of the contactors are surround by side walls which are trapezoid in section. Hence, the side walls can be readily fitted in the grooves formed along the scribing lines; that is, the semiconductors 15 can be fitted in the recesses 11 with ease. The contactor 10 and the dicing sheet having the semiconductor chips 15 are pressed against each other, so that the electrode connection is positively achieved.
    Type: Grant
    Filed: November 3, 1997
    Date of Patent: March 21, 2000
    Assignee: Matsushita Electronics Corporation
    Inventor: Katsuhiko Tsuura