Abstract: Gate and storage dielectric systems and methods of their fabrication are presented. A passivated overlayer deposited between a layer of dielectric material and a gate or first storage plate maintains a high K (dielectric constant) value of the dielectric material. The high K dielectric material forms an improved interface with a substrate or second plate. This improves dielectric system reliability and uniformity and permits greater scalability, dielectric interface compatibility, structural stability, charge control, and stoichiometric reproducibility. Furthermore, etch selectivity, low leakage current, uniform dielectric breakdown, and improved high temperature chemical passivity also result.

Abstract: Circuits and methods for driving a DRAM sense amplifier having low threshold voltage PMOS transistors are described. The source terminal of a low Vtp PMOS transistor is maintained at ground potential during DRAM standby mode. The source terminal of the low Vtp PMOS transistor is raised to an intermediate supply voltage responsive to a transition from DRAM standby mode to either DRAM read mode, write mode, or refresh mode and prior to development of a differential voltage between the gate and drain terminals of the low Vtp PMOS transistor. These circuits and methods advantageously limit current loss through the low Vtp PMOS transistor when the differential voltage develops between the gate and drain terminals of that low Vtp PMOS transistor and in the event of a word line and digital line short-circuit.

Abstract: Adaptive filters are presented that dynamically adjust the level of filtering of signals output from a sigma-delta or noise-shaping pulse code modulator RMS-to-DC converter to efficiently remove noise to improve accuracy without unduly increasing conversion response time. The level of filtering is adjusted in accordance with criteria responsive to either input signal changes (e.g., variance), input signal frequency, or both. Filtering can be analog or digital.