Abstract: A method of changing execution contexts is provided that includes receiving a context selection input. In a first clock phase, the method includes shifting data from a first latch element of a normal execution context to a second latch element of the normal execution context and shifting shadow data from a third latch element of a shadow execution context to a fourth latch element of the shadow execution context. In a second clock phase, the method includes shifting the shadow data of the fourth latch element of the shadow execution context into the first latch element of the normal execution context and shifting the data of the second latch element of the normal execution context into the third latch element of the shadow execution context. In a particular embodiment, the method may include receiving a test mode selection and shifting test data, such as scan test or automatic test pattern generated data, to a test output.

Abstract: A memory cell includes a storage element, a write circuit coupled to the storage element and a read circuit coupled to the storage element. At least a portion of the storage element and at least a portion of the write circuit are fabricated using a thicker functional gate oxide and at least a portion of the read circuit is fabricated using a thinner functional gate oxide.

Abstract: Automatic selective power and energy control of one or more processing elements matches a degree of parallelism to a monitored condition, in a highly parallel programmable data processor. For example, logic of the parallel processor detects when program operations (e.g. for a particular task or due to a detected temperature) require less than the full width of the data path. In response, the control logic automatically sets a mode of operation requiring a subset of the parallel processing capacity. At least one parallel processing element, that is not needed, can be shut down, to conserve energy and/or to reduce heating (i.e., power consumption). At a later time, when operation of the added capacity is appropriate, the logic detects the change in processing conditions and automatically sets the mode of operation to that of the wider data path, typically the full width. The mode change reactivates the previously shut-down processing element.

Abstract: A sliding-window, block-based Branch Target Address Cache (BTAC) comprises a plurality of entries, each entry associated with a block of instructions containing at least one branch instruction having been evaluated taken, and having a tag associated with the address of the first instruction in the block. The blocks each correspond to a group of instructions fetched from memory, such as an I-cache. Where a branch instruction is included in two or more fetch groups, it is also included in two or more instruction blocks associated with BTAC entries. The sliding-window, block-based BTAC allows for storing the Branch Target Address (BTA) of two or more taken branch instructions that fall in the same instruction block, without providing for multiple BTA storage space in each BTAC entry, by storing BTAC entries associated with different instruction blocks, each containing at least one of the taken branch instructions.