Abstract: A digital to analog converter utilizes two discrete time processing stages, such as switched capacitor integrator circuits, operating at different sampling rates when converting the digital input signal to an analog signal. Use of two different sampling rates relaxes the requirements on antialias filters used in the continuous time processing.

Abstract: A 1-bit digital to analog converter uses both discrete time and continuous time processing to produce an analog output signal. The analog output signal is sampled and fed back across the discrete time/continuous time interface to the input of the conversion circuit. In one implementation, the discrete time processing uses an integrator chain of switched capacitor integrators and a switched capacitor low pass filter. The continuous time processor is a 2 pole low pass filter. A finite impulse response filter can precede the discrete time processing. A plurality of analog output sampling arrangements can be selectively applied accommodate a variety of operational conditions.

Abstract: A processing system 100 is disclosed which includes a system master 101, a system bus 102 coupled to the master, and a plurality of bus interface circuits 106 coupled to bus 102. A first one of the bus interfaces 106 includes a mapping signal input coupled to the master and a mapping signal output, the first bus interface 106 operable to latch-in at least one first selected address bit presented by the master on the system bus in response to a mapping enable signal received at the mapping signal input from the master 101. A second bus interface 106 is provided coupled to the bus 102 and having a mapping signal input coupled to the mapping signal output of first bus interface 106, the second bus interface 106 operable to latch-in at least one second selected address bit presented by the master 101 on the bus 102 in response to a second mapping enable signal received at the mapping input of the second bus interface 106 from the first bus interface 106.

Abstract: A video controller for controlling at least two video displays having independent refresh rates and pixel resolutions. In a first embodiment, two separate data paths are provided within a video controller for each video display (e.g., CRT and LCD). Taking advantage of the increased bandwidth of 64 bit wide DRAMS, data for each data path may be retrieved in separate read cycles. Each datapath may operate at its own clock frequency characteristic of refresh rate and pixel resolution. The dual data path embodiment also reduces the complexity of the software model needed to drive such dual displays. IN an alternative embodiment, a single data path may be provided within a video controller to drive data for two video displays having independent refresh rates and pixel resolutions. A data "tag" (extra bit) is attached to each word or dword passing through the data path indicating the destination (e.g., CRT or LCD) of the video data. At the output of the data path, separate FIFOs (e.g.

Abstract: A technique for performing gain calibration on an analog-to-digital converter (ADC) in which offset errors are canceled during gain calibration. In an ADC having a differential integrator at the input of a modulator, two calibration measurements are obtained at the output, one based on a calibration input and the second based on the reversal of the input polarity. The two measured outputs are subtracted from each other so that offset errors introduced by the converter during gain calibration are cancelled.

Abstract: A phase comparator compares phase of a clock signal and a generated comparison clock signal based upon rising edges. The output of the phase comparator may include a series of short up (U) pulses or down (D) pulses, depending whether the phase of the comparison clock is leading or lagging the clock. Up and down pulses U and D control an up/down shift register which in turn compensates phase difference by inserting or removing additional discrete delay elements in a variable delay line. Based upon delay signals generated by the variable delay line, a double frequency clock generator generates a 2.times. clock signal. The 2.times. clock signal is divided by 2 in a divider to supply the phase comparator with the generated comparison clock signal. The feedback scheme helps the digital delay lock loop of stabilize after a few clock cycles without additional external control.

Abstract: A method of operating a multiple processor device. A first word of a sequence of words is received in a register. A target processor is determined from the first word and the target processor is interrupted. An input ready bit is set and first word from in the register is read with the target processor. A number of words in the sequence to follow the first word determined from the first word. A word counter is set and the input ready bit is cleared with the target processor. The target processor is returned to main code execution.

Abstract: Circuitry 400 remotely controls the power in a computing system. An infrared receiver 401 receives a code transmitted from a remote device 206; Circuitry 402 generates a pulse in response to the code, the pulse emulating an output of a switch 205. A transistor 403 has a control terminal for receiving the pulse and outputting a control signal in response.

Abstract: A technique for separating an operation of a digital stage into separate noise generation periods in order to time the generation of noise from the digital stage. The invention is utilized in a mixed-signal integrated circuit having analog and digital signals in which the timing of the noise generation ensures that noise is abated during an analog sampling event.

Abstract: An audio decoder 100 for operating on a received compressed audio data stream compressed using an algorithm employing transform encoding and a bit allocation routine. A first processor 200 performs a first set of operations on the received compressed audio data stream including parsing the compressed audio data stream, recovering data fields within the compressed audio data stream, calculating a bit allocation, and passing frequency domain coefficients to shared memory. A second digital signal processor 100b performs a second set of operations on data passed from the first digital signal processor to shared memory including performing inverse transform operations on the data passed from the first digital signal processor.

Abstract: Synchronization words, contained within a data transmission are detected by oversampling the incoming data transmission by a factor of M. Each of M samples are stored in a respective register on an ongoing basis and a receiver is activated to monitor the contents of all registers to determine if they contain a synchronization word. Commonly a plurality of registers may detect the presence of a synchronization word simultaneously. The one having the largest amplitude bit samples is selected and the receiver changes mode to monitor the output of that register while another receiver is activated to monitor all registers. This is particularly useful in detecting synchronization words or flags in data packets, particularly in modem to modem communications.

Abstract: A method and apparatus for coupling an External Device to a Host Computer, such that program code to be executed by the external device may be stored in the Host Computer memory and yet be essentially independent of the Host Computer. Hardware and software enable the logical displacement of a program and address bus across inter-processor interfaces. An External Device preferably provides direct access to program code stored within Host Computer memory by means of a conventional DMA function. Program code which is to be executed by the External Processor within the External Device is transferred from the Host Memory to an Instruction Buffer memory within the External Device. The External Processor determines when to request additional instructions from the Host Memory over the DMA channel on a timed interrupt basis.

Abstract: Digital-to-analog conversion circuitry 100 is shown including a path for processing data in a 1-bit format. First portion of an analog finite impulse response filter 300 includes pre-selected number of delay elements 301 for receiving stream of data in the 1-bit format and outputting a plurality of signals in response. A switched capacitor digital-to-analog converter 106 forms a second portion of the finite impulse response filter 301 and has a plurality of elements each receiving one of the plurality of signals as selected to effectuate a set of filter coefficients, converter 106 summing the plurality of signals and outputting an analog data stream.

Abstract: A method of concealing errors received in a stream of data by a multiprocessor system having a first digital signal processor for initial processing of incoming data and a second digital signal processor for processing data passed from the first processor. The method includes the steps of detecting an error in an incoming frame of the stream of data with the first processor, sending an error message from the first to the second processor, halting transmission of the remainder of the frame to the second processor, and processing a frame of dummy data with the second processor. The frame of dummy data is passed to a processing engine forming a portion of the second processor to maintain data pipelining. Interprocessor communications between the first and second processors is established by handshaking through an interprocessor communications register, wherein the first processor detects an error in a frame of data and sends a message to the second processor.

Abstract: An arithmetic and logic unit implemented in a memory array.

Abstract: A temperature compensation circuit (54 and 56, FIG. 3 ) is disclosed for maintaining the voltage at a first node. The amount of time the voltage at the first node is maintained is dependent upon the temperature of a temperature sensitive element (96). The circuit comprises a bleed-off transistor (86) and at least one temperature sensitive element (97). The first terminal (90) of the bleed-off transistor (86) is coupled to the first node and the second terminal (88) is coupled to a first voltage level. The control electrode (92) of the bleed-off transistor (86) is coupled to the first terminal (94) of the temperature sensitive element (96). The other pole of the element is coupled to a second voltage level. The element is operable to generate a voltage drop across its poles dependent upon its temperature.