Patents Represented by Attorney, Agent or Law Firm Peter Sgarbossa
  • Patent number: 6689222
    Abstract: The present invention provides such an improved metallic surface for sealable mating to a seal device such as a gasket. In one embodiment, it provides a sealable apparatus that has a component and a seal device. The component has a seal contact area for receiving the seal device. The seal contact area comprises a metallic surface with randomly distributed micro-pits that are capable of sealably mating with the seal device when the seal contact area is operably mated to the seal device.
    Type: Grant
    Filed: July 1, 2002
    Date of Patent: February 10, 2004
    Assignee: Applied Materials, Inc.
    Inventors: Don Titel, Wayne W. Wheatley, Todd W. Sharpe
  • Patent number: 6589023
    Abstract: Generally, a vacuum pumping system having efficient power usage is provided. In one embodiment, the vacuum pumping system includes a first pump, a check valve and a second pump. The check valve and second pump are coupled in parallel to an exhaust line of the first pump. The first pump and second pump have a ratio of internal volume that is about 20 to about 130. In another embodiment, the vacuum pumping system includes a first pump, a check valve and a second pump. The check valve and second pump are coupled in parallel to an exhaust line of the first pump. The first pump and second pump have a ratio of power consumption that is about 5 to about 20. In yet another embodiment, the first pump and second pump have a ratio of pumping capacity that is about 50 to about 200.
    Type: Grant
    Filed: October 9, 2001
    Date of Patent: July 8, 2003
    Assignee: Applied Materials, Inc.
    Inventors: Douglas Royce, Pedram Sabouri, Peter Reimer
  • Patent number: 5730801
    Abstract: A process chamber for semiconductor wafers is formed of multiple compartments. A first compartment is provided for supplying an isolated environment for processing the wafers, and a second compartment is provided, in selective communication with the first compartment, to load and unload wafers from the chamber. The wafer handling equipment is located in the second compartment to isolate it from the process environment, and thus form a clean, non-contaminating, environment for the wafer handling equipment. When the chamber must be cleaned, only the first compartment must be cleaned, as no processing occurs in the second chamber. Therefore, the entire first chamber may be removed for cleaning, and replaced with a clean first compartment to decrease chamber turnaround time during chamber cleaning operations.
    Type: Grant
    Filed: August 23, 1994
    Date of Patent: March 24, 1998
    Assignee: Applied Materials, Inc.
    Inventors: Avi Tepman, Gerald Zheyao Yin, Donald Olgado
  • Patent number: 5514247
    Abstract: Disclosed is a process for plasma etching a mask patterned dielectric film to form vias on a semiconductor wafer, so that the resulting etched structure is devoid of residues on the walls of the structure. A via is an opening through a dielectric material through which a point of contact of underlying metal with a metal film deposited over the dielectric is made. The underlying metal, when exposed to plasma, has a tendency to sputter onto the vertical wall portions of the contact via structures. The metal-containing sputtered material forms a residue that essentially cannot be removed in the subsequent photoresist stripping process typically used in semiconductor manufacturing. The plasma etch process in accordance with the invention enables removal of the sputtered metal by utilizing with the basic dielectric etch gases a gas that reacts with the metal to form volatile compounds which are readily evacuable.
    Type: Grant
    Filed: July 8, 1994
    Date of Patent: May 7, 1996
    Assignee: Applied Materials, Inc.
    Inventors: Hongching Shan, Robert Wu
  • Patent number: 5491603
    Abstract: The invention is embodied in a method of determining an optimum de-chucking voltage for nullifying residual electrostatic forces on a wafer in an electrostatic chuck for removal of the wafer from the chuck, including holding the wafer on the electrostatic chuck by applying an electrostatic potential to the chuck, introducing a gas between the wafer and the chuck, reducing the electrostatic potential of the chuck while observing a rate of leakage of the gas from between the wafer and the chuck, and recording as the optimum dechucking voltage the value of the electrostatic potential obtaining when the rate of leakage exceeds a predetermined threshold.
    Type: Grant
    Filed: April 28, 1994
    Date of Patent: February 13, 1996
    Assignee: Applied Materials, Inc.
    Inventors: Manoocher Birang, Jian Ding, Hyman J. Levinstein
  • Patent number: 5484486
    Abstract: This invention is directed to a novel assembly of replaceable parts for use in a substrate processing apparatus. Covers for the substrate processing surface are attached in a plurality of pieces as opposed to a solid piece, for removeability without removing the wafer support pedestals. A ring for surrounding the pedestal includes a fastener enabling the ring to snap in place onto the pedestal. A focus ring for surrounding the pedestal ring attaches to the pedestal ring via a snug fit into a built-in grooved series of notches in the pedestal ring. A novel fastener that enables two articles to snap together is disclosed.
    Type: Grant
    Filed: May 2, 1994
    Date of Patent: January 16, 1996
    Assignee: Applied Materials, Inc.
    Inventors: Greg Blackburn, Donald L. Johnson, Richard McGovern, Yan Rozenzon