Abstract: The specification describes a method for dispensing IC chips from a chip carrier tape for a flip-chip assembly operation. In a conventional assembly operation, the solder bumped side of the chip is the top side of the chip as loaded on the tape, and is normally the side of the chip that engages the head of the pick tool. For flip-chip assembly it is necessary to invert the chip for solder bonding to an interconnect substrate. In the technique of the invention, the chip carrier tape is inverted and inserted into the dispensing machine upside down. The IC chips are then ejected through the back of the tape instead of being lifted from the from of the tape. In this way the pick tool head engages the back side of the solder bumped chip and the chip is in the proper orientation for flip-chip placement and bonding on the interconnect substrate. Carrier tapes designed for through-tape dispensing are also disclosed.

Abstract: The specification describes techniques for soldering IC chips, or other components, to interconnection substrates using a patterned epoxy layer to define the solder interconnections. The epoxy layer is photodefined to form openings that expose the bonding sites on the IC chip (or alternatively the interconnect substrate). Solder paste is deposited in the openings. With the IC chip and the interconnect substrate aligned together, the solder paste is heated to reflow the solder and solder bond the IC chip to the substrate. Heating is continued to cure the epoxy, which serves the function of the conventional underfill. The shape of the solder interconnection is defined by the lithographically formed openings, and the interconnections can be made with very fine pitch. The application of the epoxy underfill in this manner assures complete filling of the gap between the IC chip and the interconnection substrate.

Abstract: The specification describes a lift-off technique useful in the manufacture of III-V semiconductor devices such as MQW lasers. The lift-off step is improved by a spacer layer of III-V semiconductor that can be non-selectively etched to form a mesa stripe, and selectively etched for the lift-off step. The spacer layer allows the etch mask to be dimensionally adjusted to reduce or eliminate overhang of the mesa, and prevent adverse shadowing effects. MBE is effective for both growing the multilayer stack and regrowing the blocking layer. A self-aligned mask on the multilayer stack can be produced by removing the overhang, and facilitating lift-off by producing an undercut in the III-V spacer layer using selective etching.

Abstract: Hydrogen Plasma surface passivation of III-V Semiconductors is critically dependent on exposure time and pressure because of competition between plasma passivation and damage. Proper control of pressure according to the invention yields reproducible and stable passivation. Improved passivation is obtained using high pressure hydrogen plasmas, i.e. above 1 Torr.

Abstract: Process for coating articles with thin film of diamond, and related diamond-like materials, using an electrophoretic technique. Diamond particles are suspended in a liquid electrolyte and subjected to a directional field which causes migration and deposition on a selected substrate electrode.

Abstract: The TVS method is a voltammetric method for detecting mobile ionic impurities in the dielectric layer of a MOS capacitor structure. Disclosed here is a method of semiconductor device fabrication involving a modified TVS method in which the voltage is changed in discrete steps rather than varied continuously, and charge, rather than induced current, is measured. The modified TVS method can be faster than conventional TVS, and calibration is unnecessary.

Abstract: In molding integrated circuit packages voids are found in the molded plastic due to air entrapped in the charging container. It was discovered that entrapped air can be avoided if a portion of the preheated charge material has a higher viscosity than the remainder. Conveniently, this is achieved by preheating the preforms in a temperature gradient and charging the hottest preforms last into the container. The pressure causes the material at the top of the chamber to flow first, thereby expelling unwanted air through the runners ahead of the plastic flow. An effective implementation results from tilting the RF electrode in the preheating apparatus.

Abstract: According to this invention, a coupler or coupling tool is proposed with active alignment of one fiber with respect to another in both planes of interest, i.e. the vertical position and the lateral position. A key feature of the alignment means is that as one position is adjusted slightly, the other position is automatically adjusted through full range. This is accomplished rapidly enough that it is simple to test all combinations of the two positions.

Abstract: Described is an improved lead design for an integrated circuit chip carrier. The lead incorporates a U- or V-bend in the portion of the lead extending along the edge of the chip carrier to adapt the lead to either surface or socket mounting. The bend can also be used for locking the lead into the socket and, in conjunction with grooves in the sidewall of the chip carrier, for lead alignment retention.

Abstract: The specification describes an improved form of heterostructure laser, termed a "Rib-Loc" laser. It is an easily fabricated device with desirable electrical and optical properties. The Rib-Loc is simple to fabricate because a single, self-aligned rib provides ohmic contact, current confinement and lateral waveguiding. A deeply etched P-cladding layer outside the rib provides the positive index change needed for an index-guided laser. The large optical cavity increases the maximum power output and reduces the aspect ratio of the beam.

Abstract: Wide temperature range magnetic bubble memories are realized by using new compositions of rare earth garnets which require nonlinear bias field for operation over a given temperature range. The bias field structure for providing the corresponding nonlinear bias field includes plates of barium ferrite plus additional plates of Ni-Cu alloys and/or polycrystalline dysprosium (or other rare earths, singly or in combination) iron garnet to provide a nonlinear bias field versus temperature characteristic to match that of the bubble layer.

Abstract: The specification describes an integrated circuit package with a lead frame that incorporates crossunder members for power distribution. It uses a paddle member for chip support and back plane contact, with crossunders extending alongside the paddle. Insulating means is interposed between the chip and the lead frame with an opening to allow contact from the chip to the paddle.

Abstract: Proposed is a new way to distribute power off chip using a specially designed lead frame. The support paddle of the lead frame is split electrically and provides at least two conductor members that are arranged to cross under the chip after the chip is bonded to the paddle. Power and/or ground can be distributed to two or more edges of the chip by providing bonding sites at or near the extremities of the crossunders. The chip itself is electrically isolated from the crossunder members.

Abstract: Described is an internally mode stabilized injection laser. Stabilization is obtained in a coupled cavity structure where one cavity is passive. The passive cavity is a high efficiency waveguide with dimensions chosen to suppress unwanted modes.

Abstract: For trench isolation technology or trench capacitor type memory cells, it is necessary to controllably dope the steep sidewalls of the trench. Implantation is ineffective and chemical doping sacrifices control.A thin transfer layer of polysilicon is deposited in the trench to conformally coat the sidewalls as well as the bottom of the trench and the top surface surrounding the trench. An impurity is implanted into the polysilicon at the bottom of the trench and around the top surface. Upon heating that impurity diffuses rapidly along the polysilicon layer inwardly and downwardly along the sidewalls. It then may be diffused into the substrate. The polysilicon layer may be etched away, or may be oxidized to SiO.sub.2 and etched away, or left in place.

Abstract: The so-called blind assembly operation involving precise registration between the blind side of chip carriers or similar macro scale subassemblies and a metallized (patterned) support member requires improvements to reduce packaging costs. The proposal is to form indents aligned in both mating surfaces and place an aligning ball in the lower indent. The upper surface is positioned approximately and manipulated in x and y directions until the alignment ball recesses into both indents.

Abstract: The specification describes a process for treating patterned VLSI lithographic masks to retain their shape during processing of VLSI wafers. The process avoids the common postbake treatment which tends to cause sagging of the sidewalls of the mask. Retention of vertical sidewalls on the mask edges has been found important for producing vertical sidewalls in layers that are being anisotropically etched.

Abstract: The specification describes a technique for etching titanium using EDTA compounds. It is especially useful for selective etch processes such as those used to form titanium diffused waveguides in lithium niobate crystals.

Abstract: A transfer layer is utilized to laterally redistribute impurities from a more heavily doped region to a lighter doped region. The contact to the source-drain region in advanced memory arrays has a width of the order of the minimum feature size. The source-drain has similar minimum feature dimensions in width to keep the array optimally dense. Thus this contact is made "headless" and requires a "line on line" alignment. Some offset in forming the window is inevitable and that offset exposes the channel stop. The contact then shorts to the substrate.Using a polysilicon transfer layer with an appropriate post anneal the region immediately under the contact and along the window sidewall can be autodoped sufficiently to avoid shorts to the substrate, and provide a continuous electrical path for the deposited contact.

Abstract: A dynamic random access memory in which individual cells, including an access transistor and a storage capacitor, are formed in mesas formed on a silicon chip. The access transistor of the cell is formed on the top surface of the mess and one plate of the storage capacitor of the cell is formed by the sidewall of the mesa and the other plate by doped polycrystalline silicon which fills the grooves surrounding the mesas isolated therefrom by a silicon dioxide layer. By this geometry, large storage surfaces, and so large capacitances, can be obtained for the capacitor without using surface area of the chip. In other embodiments, the mesas may include other forms of circuit elements.