Abstract: A gun operating system for firearms, particularly for a shotgun, includes a bolt/slide movable between a closed position prior to firing and an open position after firing and a link operatively connected to the bolt/slide. An inertial recoil assembly housed in the gun stock is operatively connected to the link and includes a first mechanical an/or gas spring having a higher spring deformation rate in series with a second mechanical spring having a lower spring deformation rate. Upon firing of the gun, the bolt/slide is adapted to move to the open position and the link is adapted to initially deform the first spring in one direction and, subsequently, the first spring is adapted to return to its initial position and move the link and deform the second spring in the opposite direction.

Abstract: A safety and bolt assembly system for firearms, particularly for a shotgun. A firing pin is slideable within an opening in the gun's bolt to strike a shell in the gun. The firing pin being movable between a first position in which it is aligned with the opening and capable of sliding movement to strike the shell and a second position in which it is out of alignment with the opening and incapable of sliding movement to strike the shell. The gun safety system includes a spring for urging the firing pin away from the shell and an angled slot for moving and retaining the firing pin away from the shell when the bolt is in the second position. A link is adapted to connect the bolt/slide to a bolt operating system, a pin is secured to one of the bolt/slide or link, and a slot is present in the other of the bolt/slide or link to receive the pin. The slot is angled rearward to prevent movement of the pin from the slot during movement of the bolt/slide in the direction of the link.

Abstract: A method of determining bias or overlay error in a substrate formed by a lithographic process uses a pair of straight vernier arrays of parallel elements, a staggered vernier array of parallel elements, and optionally at least one image shortening array on the substrate. The ends of the elements form the array edges. The vernier arrays are overlaid such that: i) the elements of the straight and staggered arrays are substantially parallel; ii) one of the edges of the staggered array intersects with one of the edges of one the straight arrays; and iii) the other of the edges of the staggered array intersects with one of the edges of the other of the straight arrays.

Abstract: A method for mapping a surface adapted for receiving electrical components comprising the steps or providing a probe having a plurality of contacts, moving the probe toward the surface at a predetermined rate of speed, recording the time of all occurrences of contact between each of the probe contacts and the surface, determining the height of each portion of the surface contacted by one of the probe contacts, and correcting the height to account for non-planarity of the probe contacts.

Abstract: An efficient method of selecting flip-flops to be made scannable in a digital integrated circuit design for purposes of improving testability without incurring the overhead of full-scan, comprising the steps of (a) partitioning the faults in the circuit into a first fault type and a second fault type, (b) selecting a static characterization algorithm for characterizing the first and second fault types, (c) determining the relationship between attainable fault coverage and the characterized values for the first and second fault types, (d) characterizing the first and second fault types for each candidate flip-flop for scan in the digital integrated circuit with the static characterization algorithm, (e) determining the first and second fault types that are the closest together in value, (f) selecting the flip-flop associated with the first and second fault types determined in step (e), (g) forming a shift register with flip-flop selected in step (f), (h) repeating steps (d)-(g) until the attainable fault cover

Abstract: A programmable serializer comprising a multi-bit input port, a multi-bit output port, at least one multiplexer and at least one programmable address counter corresponding to the multiplexer for generating a sequence of multiplexer data input addresses that are inputted into the multiplexer address input. The multiplexer has an output connected to the multi-bit output port, an address input and a plurality of data input channels having addresses. Each data input channel is connected to a corresponding bit of the multi-bit input port. At least one data input channel is coupled to the multiplexer output when the corresponding address of the data input channel is applied to the address input. The programmable address counter receives and stores an initial address value, an address increment value and a count value and generates a sequence of addresses based on these values. The initial address value represents the multiplexer data channel that is to be initially coupled to the multiplexer output.

Abstract: A process for fabricating a high density memory array. N-type impurities are implanted in a p-type substrate to form continuous rails of diffusion that have a substantially flat contour. Each rail of diffusion defines a corresponding bit line. Each rail defines the source and drain region of each pair of adjacent memory array cells associated with the bit line. In one embodiment, multiple layers of polysilicon are utilized to form a control gate, a floating gate, a source and a drain. In another embodiment, multiple layers of polysilicon are utilized to form an auxiliary gate, a floating gate, a source and a drain. In both embodiments, the polysilicon layers self-aligned to substantially reduce polysilicon layer-overlap so as to minimize parasitic capacitances. Domino and Skippy Domino schemes are used to program and read the memory array cells.

Abstract: A process and system for effecting addition and/or subtraction any two symbols having any number of characters and in any base with full precision and without first converting to a common base. Regardless of the quantity of characters of each symbol, the speed of execution remains almost constant per character. The process and system of the present invention does not require the use of floating point notation. Furthermore, the process and system of the present invention does not require or use standard mathematical algorithms, addition or subtraction tables, or exponentiation.

Abstract: A process for fabricating a high density memory array. N-type impurities are implanted in a p-type substrate to form continuous rails of diffusion that have a substantially flat contour. Each rail of diffusion defines a corresponding bit line. Each rail defines the source and drain region of each pair of adjacent memory array cells associated with the bit line. In one embodiment, multiple layers of polysilicon are utilized to form a control gate, a floating gate, a source and a drain. In another embodiment, multiple layers of polysilicon are utilized to form an auxiliary gate, a floating gate, a source and a drain. In both embodiments, the polysilicon layers self-aligned to substantially reduce polysilicon layer-overlap so as to minimize parasitic capacitances. Domino and Skippy Domino schemes are used to program and read the memory array cells.