Abstract: A process of merging an original drawing file and at least one updated or modified drawing file based on the original drawing file to produce a common or merged drawing file. The original drawing file and the updated drawing file are first stored in a storage medium and then merged. The entities of the original and updated drawings are then compared for duplicate entities and modified entities. Entities of the original drawing that are duplicated in the updated drawing are automatically removed. Entities of the original drawing that have been modified in the updated drawing are also automatically removed.

Abstract: A desired design for electronic structures is converted into a graphic design format and sorted into a pseudo-raster format corresponding to scan lines. A laser or other machining beam is controlled by a separate tracking beam utilizing a mid-objective scanning system. The firing frequency of the machining beam is determined by the position of the tracking beam on a detector, as compared to the scan line data. Accuracy is verified by detection of plume or spectra generated during machining. Evaluation and alignment of the machining and tracking beams is by interferometric methods. The system improves optical performance parameters of telecentricity, angle of scanned beam line, location of line in which the scanned line resides, astigmatism and field curvature.

Abstract: A process for fabricating a high density memory array. N-type impurities are implanted in a p-type substrate to form continuous rails of diffusion that have a substantially flat contour. Each rail of diffusion defines a corresponding bit line. Each rail defines the source and drain region of each pair of adjacent memory array cells associated with the bit line. In one embodiment, multiple layers of polysilicon are utilized to form a control gate, a floating gate, a source and a drain. In another embodiment, multiple layers of polysilicon are utilized to form an auxiliary gate, a floating gate, a source and a drain. In both embodiments, the polysilicon layers self-aligned to substantially reduce polysilicon layer-overlap so as to minimize parasitic capacitances. Domino and Skippy Domino schemes are used to program and read the memory array cells.

Abstract: A process for transferring a thin film wiring layer to a substrate in the construction of multilayer chip modules initially provides a sacrificial release layer formed on a surface of a carrier. Directly on the release layer there is formed in inverted fashion a plurality of multilevel thin film structures having at least one wiring path of metallic material exposed on the surface opposite the carrier. An electronic packaging substrate is provided, and solder or other joining material is applied to one or both of the exposed metallic surface of the multilevel thin film structure or the substrate. The multilevel thin film structure is then joined to the substrate so that the attached carrier is remote from the substrate. The release layer is subsequently contacted with an etchant for the release layer so as to remove the carrier from the multilevel thin film structure to produce a multilayer chip module.

Abstract: An electrical probe card for parametric testing of microelectronics having reduced leakage current, includes a hydrophobic layer of a self curing silicone material coating the entire exposed surface of the ceramic card between exposed conductors. The hydrophobic layer has a thickness of less than 1 micrometer, preferably less than 0.1 micrometer and most preferably between 0.01 and 0.001 micrometers. The hydrophobic layer does not interfere with subsequent soldering to the contacts on the card, is inexpensive, solvent resistant and easily applied to new and pre-existing probe cards. The method of application involves applying an excess of the hydrophobic silicone material in its uncured state, followed by vigorously wiping excess material off to thin the layer, produce a good bond and clean the exposed conductors on the probe card.

Abstract: A method for restructuring information stored in physical design image form, such as an image of a layer in a semiconductor package, into a hierarchical area specification model useful in automated design applications. The restructuring results in recognizing identical patterns in the image and storing common information about the patterns in a single location to decrease storage space required and improve access efficiency by design application programs needing the information. Parameters controlling the method can be adjusted to produce a hierarchical model that is particularly suited to the needs of a particular application program.

Abstract: A thermal conduction module comprises a base plate for holding a chip substrate, an integrated circuit chip substrate mounted in the base plate and a cover plate having a surface facing the chip substrate. A movable spacer is secured adjacent to the periphery of the cover plate or the base plate, and is adjustable to a predetermined distance away from the cover plate or base plate. A gap for insertion of a thermally conductive paste may be created between chips mounted on the substrate and the cover plate surface facing the chip substrate by adjustment of the spacer to a desired distance from the cover plate or base plate.