Abstract: A method for efficient coding of non-active voice periods is disclosed for a speech communication system with (a) a speech encoder, (b) a communication channel and (c) a speech decoder. The method intermittently sends some information about the background noise when necessary in order to give a better quality of overall speech when non-active voice frames are detected. The coding efficiency of the non-active voice frames can achieved by coding the energy of the frame and its spectrum with as few as 15 bits. These bits are not automatically transmitted whenever there is a non-active voice detection. Rather, the bits are transmitted only when an appreciable change has been detected with respect to the last time a non-active voice frame was sent. To appreciate the benefits of the present invention, a good overall quality can be achieved at rate as low as 4 kb/s on the average during normal speech conversation.

Abstract: A circuit for resetting an electronic system based on voltage fluctuations in the power supply is disclosed. The circuit comprises a diode means for generating a first voltage being offset from the supply voltage, a first inverter having its input connected to the diode and powered by a reference voltage source, a second inverter having its input connected to the same reference voltage source and powered by the power supply; and an OR- or NOR- gate having its inputs from the outputs of the first and second inverters, such that its output, when asserted, resets the electronic system.

Abstract: A single clamp circuit for integrated circuits with multiple V.sub.dd power pins by coupling the various V.sub.dd busses to an ESD clamped V.sub.dd bus or pseudo- V.sub.dd bus via diodes. The diodes will provide coupling from any V.sub.dd bus to the clamp circuit during a positive ESD transient. A diode for each V.sub.dd bus and a single clamp circuit can be much more area efficient than a single clamp circuit for each V.sub.dd bus. During normal operation, the diodes will become weakly forward biased due to the leakage current of the clamp circuit. Small signal noise will tend not to be coupled from one bus to the other because of the high impedance of the diodes. For a large positive noise transient on one bus, the other bus diode will reverse bias, thus decoupling the signal from the other busses. A large negative noise transient on one bus will cause its diode to reverse bias thus decoupling it from the other busses.

Abstract: A register file connected to a data memory and an arithmetic logic unit for temporary storage of operands, and a method of managing such register file permits the register file to be used to maximum efficiency, and permits rapid task and context switching. Each register of the register file has an absolute address. A relative register address is read from the address field of the instruction being executed by the ALU, and an arithmetic calculation is performed on that relative register address and a register base address to obtain an absolute register address of the register to be accessed. Different sets of registers may be designated for different tasks or contexts. Each set of registers has its own base address. Once the task or context to which the instruction applies is determined, a calculation using the relative address from the instruction address field, and the corresponding register set base address may be performed to obtain the absolute address of the register to be accessed.

Abstract: A fleet management system for a base station to obtain differential GPS corrections to the location information for the fleet vehicles. A fleet vehicle first sends the information of "position solution" back to the base station with time annotation, where the position solution only needs to specify position, velocity and the satellites observed. The base station, which already has an a priori fixed position vector for its location, generates a potential solution set for all the possibly observable satellites. This allows the base station to vector-process to determine the differential correction for each combinatorial set of satellites observed by the fleet vehicle. This way, equivalent differential GPS accuracy of 10 meters or better can be achieved for the fleet management system without imposing the communications burden to the system.

Abstract: A differential amplifier with improved offset cancellation is disclosed. The differential amplifier has a floating current source coupled to the drain terminals of the differential pair for providing complementary currents to cancel the offset voltage. In this way, the tail current in the differential pair is not affected by the offset cancellation and remains constant, while the common-mode offset is not worsened by the injected current.

Abstract: A converter for converting a single-ended input V.sub.IN to a differential output signal V.sub.OUT through positive and negative output terminals is disclosed. The converter comprises a fully differential amplifier with one of its input terminals coupled to the single-ended input and its other input terminal coupled to a fixed voltage. The converter also has a first resistor ("R.sub.1 ") coupled between the single-ended input and the positive input terminal of the fully differential amplifier, a second resistor ("R.sub.2 ") coupled between the fixed voltage and the negative input terminal of the fully differential amplifier, a third resistor ("R.sub.3 ") coupled between the positive input terminal and the negative output terminal of the fully differential amplifier, and a fourth resistor ("R.sub.

Abstract: A method and apparatus for a decision-directed timing recovery scheme to stabilize its equalizer positioning by centering equalizer taps is disclosed. First, the measure of equalizer positioning is calculated. The measure is then scaled to generate a timing bias signal. The timing bias signal is used to shift the timing phase of the equalizer input.

Abstract: An on-board regulated voltage up-convertor for converting a first DC voltage at a first node from an electronic system to a second DC voltage for an integrated device at a second node. The convertor comprises reference generator means for generating a predetermined reference voltage at start-up, voltage regulator means coupled to said first node for regulating said first voltage at a predetermined voltage at a third node, voltage multiplier means coupled to said third node and to said second node for multiplying said predetermined voltage to generate an output voltage substantially equal to said second voltage, feedback means coupled to said second node for feeding said output voltage back to said voltage regulator means to adjust the level of said predetermined voltage at said third node according to how said output voltage is relative to said second voltage.

Abstract: A circuit for converting a system supply voltage having one of two levels to a voltage for use by an integrated analog circuit connected to the system upon power-up. The circuit uses a diode-connected transistor to generate a reference voltage necessary for a regulator to regulate the supply voltage when the supply voltage is first powered up. The regulated supply voltage is doubled to a voltage level sufficient to activate the integrated analog circuit's bandgap voltage. The activated bandgap voltage is thus switched on to supply a more precise reference voltage to the regulator so that the diode-connected transistor may be de-activated to conserve power. The circuit also provides a bypass path for connecting the supply voltage directly to the integrated analog circuit when the supply voltage is the same level as the necessary voltage for the integrated analog circuit.

Abstract: A modular radar system using both FM/CW and pulse waveforms for automotive collision avoidance applications.

Abstract: A novel supply discriminator circuit is disclosed for detecting the level of a supply voltage during power-up of a system for configuring an integrated analog circuit such as a PCMCIA card. The circuit compares a reference voltage with a divided down supply voltage and latches the result a predetermined delay later. The delay thus provides timing for the supply voltage to stabilize after power-up to assure accurate detection, as well as noise immunity from other devices.

Abstract: A circuit for detecting a system reset caused by the turning on of power supply of an electronic system. The circuit comprises: latch means coupled to said power supply having a SET input and an output, said output of said latch means being reset to a first predetermined state during power-on; feedback means for receiving said output from said latch means and said system reset, said feedback means activating its output when both of said first predetermined state from said latch means' output and said system reset are present; delay means coupled to the output from said feedback means and to said latch means, said delay means activating its output a predetermined time after said delay means receiving an activated output from said feedback means, said activated output from said delay means setting said latch means to a second predetermined state such that said feedback means remains de-activated when only said system reset is present without power-on.

Abstract: A variable multi-threshold detection circuit for a sampled baseband signal in the receiver of a communication system using GMSK modulation is disclosed. The circuit comprises an integrate/dump circuit for accumulating a predetermined number of samples of the baseband signal to generate a sum for a present bit, a level selector for selecting a threshold from a plurality of groups of multi-thresholds based on an estimated phase offset and the binary value of two previous bits, a compare circuit for comparing the sum from the integrate/dump circuit with the threshold selected from the level selector to generate a binary value of either one of "0" or "1" for the present bit, and a delay circuit for delaying the present bit to be used by the level selector to determine a next threshold for a next bit.

Abstract: An apparatus and method for converting a charge packet into digital bit weights. The apparatus comprises a plurality of serially connected charge-coupled cells for receiving the charge packet at one end, such that the charge packet consecutively fills each CCD in the path. Also, a detector is coupled to another end of the CCD's for advancing charge within the CCD's and detecting whether each CCD is filled. A counter coupled to the detector for counting the number of CCD's which are not filled with charge, wherein the number represents a first form of digital bit weights of the charge packet.

Abstract: An adaptive timing recovery method and apparatus are disclosed. The present invention reduces the problems in connection with the conventional timing recovery by varying the gain of the band-edge filtering in inverse proportion to the available band-edge energy in the received signal. The non-linearized outputs from the "early-late" filter are first added together and then subtracted from a reference value. A small fraction of the result is subtracted from the filter gains of the two half-symbol-rate filters. Therefore, if the band-edge energy is small, then the sum of the non-linearized outputs is negative and the timing filter gain values are increased. If the band-edge energy is large, then the filter gains will be reduced.

Abstract: An ESD protection circuit for the pads of an integrated circuit (IC) using silicide-clad diffusions is disclosed. The circuit uses a robust N+ diode with N-well block, an output NFET and a large transient clamp, each with a distributed, integrated N-well drain resistor to prevent the IC from avalanching and leakage during the Human Body Model and Charged Device Model tests for ESD.

Abstract: Low time-bandwidth product linear frequency modulated chirp pulses are repetitively generated as contiguous subpulses to form a pulse of extended duration with each subpulse respectively mixed with one of a plurality of stepped intermediated frequencies so that the bandwidth of the contiguous subpulses is increased to the frequency bandwidth of all of the stepped intermediate frequencies such that the contiguous signal formed has a linearly varying frequency over the increased bandwidth and increased pulse duration, providing a large time-bandwidth product linear frequency modulated chirp waveform particularly useful in radar systems.

Abstract: A device and method for controlling the gain of a charge based signal is described. The described device and method may be used for both offset correction and for gain control. First and second charge holding gates are provided for receiving a charge packet representing a signal. A control gate partitions off at least a portion of the charge on the secondary charge holding gate. The charge not so partitioned off is then transferred onto the output line as the adjusted charge packet representing the adjusted signal, where the gain is now the ratio of areas of first charge holding gate to the sum of areas of both first and second charge holding gates. The offset of a signal can also be corrected by segregating the portion of charge representing the offset of an input signal onto the second charge holding gate.

Abstract: A dynamically tunable notch filter is used within a continuously transmitting laser radar system for filtering narcissus signals generated from a continuous linear frequency modulated chirp transmission signal at the transmission aperture antenna with the filter including mixing and band pass filtering at the narcissus dynamic frequency to eliminate the unwanted narcissus signals varying over the dynamic frequency range of the narcissus signals, and to also eliminate unwanted target images, for improved resolution and detection of low level reflected target signals which are often obscured by the presence of the relatively high-level unwanted narcissus signals.