Abstract: A portable security system is based on maintaining wireless communication between two or more plastic cards within a defined range. In the simplest form, a first card intermittently transmits an identification code to a second card. The second card compares that code with a code in an internal register, and on matching those codes, transmits a return code to the first card. The first card compares the return code with a code in an internal register, and on matching those codes, resets a timer. If the timer is not reset during a defined number of transmissions by the first card, an alarm circuit is activated. One card is attached to a valuable object such as a wallet on the person, and the other card is placed elsewhere on the person; theft of the object from the person results in activation of the alarm circuit. In an advanced form, a master card communicates with a series of slave cards; each of the slave cards is attached to a different valuable object on the person.

Abstract: A system for the automated transfer of data includes a means for transmitting a paper form by telephone, a means for receiving the transmitted image of that form, and a computer connected to the receiving means. The format on the paper form is prepared using a program on the computer, and a copy of that format is stored in the computer. The format includes option boxes, alphanumeric blocks for specific data collection and blank figure-8 boxes for collecting numerical information. An operator of the computer selects the particular format required according to the needs of the location(s) having the transmitting means. The format is then transmitted to the location(s) either physically as a paper form or electronically over the telephone. Personnel at the location(s) select from the various options on the paper form, and return an image of the form by telephone to the receiving means.

Abstract: An engine system using refrigerant fluid is capable of utilizing the heat produced by an external high-efficiency hydrocarbon fuel combustion process. The heat from that process is utilized to transform the refrigerant fluid from a liquid state to a gaseous state in a cycle which includes extracting work from the fluid in the gaseous state in a high-compression-ratio piston engine. The cycle further includes transforming the fluid in the gaseous state back to the liquid state in a condenser, and then feeding that fluid under pressure to a heating chamber where the combustion process heat again returns it to the gaseous state at high pressure and temperature. The engine system has a higher efficiency than hydrocarbon fuel combustion engines, and has particular application to use in automobiles. One preferred refrigerant fluid for this engine system is 2,2,Dichloro-1,1,1,Trifluoro-Ethane.

Abstract: A snowplow deflector assembly is attachable to that type of snowplow which is mounted on the front end of a vehicle. The deflector assembly comprises a deflector member which is supported to extend over the top of the blade of the snowplow to deflect snow moving off the top of the blade, that snow being thereby substantially prevented from being thrown against the windshield of the vehicle and obstructing the view of a driver. Two embodiments of the invention are described.

Abstract: A BiCMOS logic circuit with Schottky-diode emulator is formed from three NMOS field-effect transistors, a PMOS field-effect transistor, a npn bipolar transistor and a load element. First and second NMOS transistors and the PMOS transistor are connected serially between ground and a positive supply voltage. The input signal to the circuit is connected to the gate of the first NMOS transistor and the gate of the PMOS transistor, each of which sits on an opposite side of the second NMOS transistor. The drain and gate of the second NMOS transistor are connected to each other and to the drain and gate of the third NMOS transistor. The drain of the first NMOS transistor is connected to the base of the npn transistor, which has its collector connected through a load to the supply voltage. The source of the third NMOS transistor is also connected to the collector of the npn transistor.

Abstract: Programmable logic array, multiplexer and memory array circuits utilizing the dynamic CMOS logic of the invention are capable of operating at speeds approximating twice that of similar circuits utilizing conventional dynamic CMOs logic. The circuit of the invention has an AND plane defined by a series of input columns and a series of rows, and has an OR plane defined by the series of rows and one or more output columns. Transistors are connected selectively between the input columns and the rows, and between the output columns and the rows. During one state of an external clock input to the circuit, each of a series of inputs are placed on a respective one of the input columns, each of the output columns are precharged, and each of the rows is discharged. The shifting of the external clock input to the alternate state results in latching of the values on the input columns and in termination of the output column precharging and row discharging.

Abstract: A testing circuit interfaces serially with the data path of an embedded memory circuit formed from at least one memory unit having separated data input and output lines and tandem addressing. Part of the testing circuit is a series of two-input multiplexer units which are adapted to be embedded on the same chip as the memory circuit. The outputs of the multiplexer units connect to a respective one of the data input lines of the memory circuit. Excepting the first bit position, a first input of each multiplexer unit is adapted to connect to the data output line of the adjacent bit position in the memory circuit. The second inputs of the multiplexer units are adapted to connect to the data bus of the chip. A further part of the testing circuit is a finite state machine which is adapted to connect to the first input of the multiplexer unit at the first bit position and to the data output line at the least bit position.

Abstract: A multilayer thick film package for housing a microchip is formed from a series of insulating wafers. A wafer adapted to occupy an outer position on the package has a first series of apertures positioned to correspond with the placement of pins on the package, and wafers adapted to occupy inner positions on the package each have a second series of apertures. The second series of apertures is comprised of apertures that correspond in position to the first series of apertures, but is also comprised of additional apertures. Conductive material in the additional apertures allows electrical connection to be made within the package to the conductive lines that extend from the pins of the package to the inner package interface adapted to abut to a microchip. Two forms of the electrical connections are discussed.

Abstract: A grating is positioned on a surface acoustic wave device on a first axis in-line with the delay line for substantially reducing the amount of energy reflected on that axis to the transmitter and receiver. The grating site on the first axis at a position between the delay line and one of the edges of the device. The grating is comprised of a parallel series of grating members each oriented so as to extend at a first angle relative to the first axis, the grating members being generally longitudinally bisected by that axis. An optimum value for the first angle is provided by a theoretical analysis, and experimental results are presented. On the experimental device, the grating is defined by a series of parallel grooves formed in the surface of the device; however, the grating may also be defined by a series of metallic strips mounted on the surface of the device.

Abstract: A solid state switching device allows independent control of the latching and holding currents, and has particular application to telephone systems. The holding current may be set at a high level so as to return the switching device to the off-state without a large reduction in the current to the circuit embodying the switching device, whereas the latching current may be set at a low level to reduce the heat dissipation in the device just prior to the transition from the latching state to the holding state. The device, which may be implemented in either linear technology or with discrete components, is a thyristor structure defined by npn and pnp bipolar transistor devices each having its base connected to the collector of the other. Each transistor device has a resistance between its base and emitter, and in the case of at least one of the transistor devices that resistance varies with the voltage on the collector of the associated transistor device.

Abstract: An interrupted liquid phase epitaxy process for producing distributed feedback laser wafers involves epitaxial growth at a first temperature range followed by epitaxial growth at a second higher temperature range. A prior art liquid phase epitaxy process involves a low temperature soak at a temperature of approximately 615 degrees Centrigrade followed by ramped cooling and epitaxial growth of a guiding layer, active layer and confining layer at a temperature of approximately 595 degrees Centigrade. The interrupted liquid phase epitaxy process involves epitaxial growth of a guiding layer in a manner similar to the prior art process, but growth of the guiding layer is followed by a high temperature soak at a temperature of approximately 645 degrees Centrigrade. Ramped cooling follows, with epitaxial growth of the active layer and confining layer taking place at a temperature of approximately 628 degrees Centigrade.

Abstract: Telephone numbers are stored and retrieved for automatic redialling by an arrangement that includes a memory map of bits. Each bit is uniquely associated with a respective redial key and a respective memory bank of the arrangement. Each memory bank has a capacity sufficient to store a telephone number. Actuation of a predefined one of the redial keys always results in redialling of the last telephone number stored. If one of the other redial keys is actuated after telephone dialling, a memory management unit of the arrangement assigns a first value to the bit uniquely associated with that key and an available memory bank. Subsequent actuation of that other key then results in automatic redialling of the telephone number associated with that key. In a further form of the invention, one of the other redial keys may be actuated during, rather than after, dialling of the telephone number.

Abstract: Tuning elements are mounted on a coplanar waveguide probe adapted to be used for on-wafer microwave noise measurement of integrated circuit devices. Each of the tuning elements is a capacitive varactor which is connected between a respective position on the input signal line of the probe and a respective capacitor to ground for the injection of bias voltage. The input signal line carries a gate voltage for the wafer device under test, and the differential voltage between the gate voltage and the bias voltage applied to the respective varactor determines the capacitance presented to the signal line by the varactor. The impedance of the signal line at the point where the probe contacts the wafer can be varied by adjusting the bias voltages applied to the varactors. The position at which each of the varactors is connected to the input signal line depends upon the wavelength of the input signal and is normally less than two wavelengths of the input signal from the end of the probe that contacts the wafer.

Abstract: A circuit for protecting sensitive telephone equipment from voltage or current overloads on the TIP or RING line includes a resistor serially positioned in the line and a triac triggered by a voltage differential across the resistor. A pair of fast diodes is positioned on the line adjacent to the telephone equipment for momentarily clamping the voltage on the line at that point between ground and the voltage supply of the equipment. The mementary clamping of the voltage creates the voltage differential across the resistor which triggers the triac. The fast diodes are capable of passing current for a time sufficient to allow the triac to begin shunting current to ground. An enhanced form of the protection circuit includes a second pair of diodes extending in parallel with the fast pair of diodes and positioned on the line between the pair of fast diodes and the triac. Inclusion of the second pair of diodes allows the circuit to utilize a triac with a slower turn-on time and a higher on-state voltage.

Abstract: Current-mirror circuitry is utilized on a MOS integrated circuit for regulating the amount of current entering the pre-charged nodes of a pre-charged logic circuit. The current-mirror circuitry involves a series of bias transistors, each extending in parallel with a respective one of the pre-charge transistors, and a bias current circuit. The bias current circuit is formed by a transistor and a resistance element which are serially connected across the power supply of the logic circuit. The gate of the bias circuit transistor is connected to the gates of the bias transistors, and the current passing through each bias transistor depends upon the relative dimensions between that transistor and the respective bias circuit transistor. The value of the resistance element determines the amount of current passing through the bias circuit transistor and therefore through the bias transistors.