Abstract: A charge pump system, including a charge pump and associated distributed clock generation circuitry, is provided for generating high voltages from a low initial voltage in applications such as erasing and programming electrically erasable programmable read only memory (EEPROM) arrays. The charge pump system uses a power supply voltage and a clock and includes a first phase bootstrapping circuit, an inverter, and a second phase bootstrapping circuit, and a two-stage charge pump. The two phase bootstrapping circuits are both responsive to the clock and use a distributed bootstrapping scheme to provide first and second phase clock signals with fixed multiples of the power supply voltage in order to overcome increased effective transistor threshold voltages, increase efficiency, and allow for charge boosting in a limited number of stages. The inverter is connected to the second phase bootstrapping circuit, causing the second phase clock signal to be opposite in phase from the first clock signal.

Abstract: A distributed collaborative computer system is provided that comprises a plurality of server computers interconnected via a high-speed link. Client computers can connect to any available server computer and start or join a conference hosted on either the server computer to which the client computer is connected or any other server in the system. As a result, the system and method of the present invention is easily scalable to support an arbitrary number of participants to a conference by merely adding the appropriate number of server computers to the system. In addition, by replicating the conference information on more than one server computer, the single point of failure limitation is eliminated. In fact, if a server hosting or participating in a conference malfunctions, the failure is detected by other server computers and the client computer is able to reconnect to the conference through a new server computer.

Abstract: A charge pump system and associated variable-amplitude clock generation circuitry are provided for generating high voltages from a low initial voltage in applications such as erasing and programming electrically erasable programmable read only memory (EEPROM) arrays. The charge pump system uses a power supply voltage and a clock and includes a first phase bootstrapping circuit, an inverter, and a second phase bootstrapping circuit, and charge pump circuitry. The two phase bootstrapping circuits are both responsive to the clock and provide first and second phase clock signals. The inverter is connected to the second phase bootstrapping circuit, causing the second phase clock signal to be opposite in phase from the first clock signal. The charge pump circuitry is responsive to the power supply voltage and the first and second phase clocks and uses native transistors that have lower threshold voltages.

Abstract: Short pseudo-random (PR) probing sequences that comply with ITU V.90 digital impairment learning (DIL) descriptors provide DIL probing sequences that yield high performance in severe inter-symbol interference (ISI) channels. The short PR sequences do not require the insertion of extra zero symbols to get rid of ISI. Further, a novel receiving structure corrects for propagation of digital impairment common in conventional equalizers for an ISI free receipt of the probing sequences within the strictly time constrained probing sequence. Based on the reliably received signals, general digital impairment mapping tables, digital pads, regular and strange RBS patterns, and different types of PCM codecs (A-law/&mgr;-law) are identified.

Abstract: A complementary dynamically controlled differential amplifier provides an accurate analog input for rail-to-rail common mode inputs. In an embodiment, the amplifier comprises two complementary difference circuits. Each difference circuit has a biasing and gain control section comprising an primary differential amplifier, a crossover differential amplifier, and associated current sources and resistors. Each crossover differential amplifier pair is driven by the output of the complementary difference circuit, with the output of each difference circuit being level shifted prior to driving the crossover differential amplifier pair of the complementary difference circuit. A level shifting section in each difference circuit performs this level shifting function.

Abstract: A computer system with densely-mounted components and effective cooling is provided. A hard drive mounting structure for “hot swap” hard drives utilizes a hard drive assembly in which a hard drive is mounted between a pair of parallel rails connected by a retaining portion. The rails provide a precise mechanism for loading and unloading the “hot swap” drive, without increasing the overall height of each hard drive assembly. A handle with double-cam actuation is used during insertion and removal of the hard drive assembly. In accordance with the present invention, two half-height hard drives may be stacked in a server mountable in a 2U rack. A tool-less lock is provided for releasably securing expansion cards to the computer case without the use of screws.

Abstract: An I/O interface circuit includes an output buffer circuit and an input buffer circuit. The output buffer circuit can receive a first stream of data elements for output from the semiconductor chip, add a separate reference element for each data element in the first stream, and generate a first data transmission signal representing the data elements of the first stream and the respective reference elements. The input buffer circuit can receive a second data transmission signal representing data elements of a second stream and respective reference elements for the data elements of the second stream, sample the second data transmission signal to obtain voltage values for each data element of the second stream and the respective reference element, and interpret the voltage value for each data element of the second stream against the voltage value for the respective reference element in order to recover the data elements of the second stream.

Abstract: An amplifier circuit comprising an input stage capable of receiving and amplifying an input signal, a gain stage electrically coupled to the input stage that is capable of further amplifying the input signal, and an output stage electrically coupled to the gain stage that is capable of charging a capacitance of the amplifier circuit and outputting the amplified input signal. The gain stage of the amplifier circuit comprises a pair of gain transistors with base terminals that are electrically coupled to the input stage, collector terminals that are electrically coupled to a path to ground, and emitter terminals that are electrically coupled to the output stage.

Abstract: A charge pump system includes a charge pumping circuit for outputting a high voltage VPP at a node. An oscillator circuit, coupled to the charge pumping circuit, drives the charge pumping circuit with at least one clock signal. A current source generates a pulldown current. A voltage divider circuit is coupled between the node and the current source. The voltage divider circuit cooperates with the current source to form a feedback loop for controlling the oscillator circuit to run at variable, optimum frequency for controlling the rate-of-rise and the amplitude of the high voltage VPP while minimizing power-supply current drain.

Abstract: A silicon carbon nitride (SiCN) layer is provided which has a low leakage current and is effective in preventing the migration or diffusion of metal or copper atoms through the SiCN layer. The SiCN layer can be used as a diffusion barrier between a metal portion (such as a copper line or via) and an insulating dielectric to prevent metal atom diffusion into the dielectric. The SiCN layer can also be used as an etchstop or passivation layer. The SiCN layer can be applied in a variety ways, including PECVD (e.g., using SiH4, CH4, and NH3) and HDP CVD (e.g., using SiH4, C2H2, and N2).

Abstract: A novel hollow cathode magnetron source is disclosed. The source comprises a hollow cathode with a non-planar target. By using a magnet between the cathode and a substrate, plasma can be controlled to achieve high ionization levels, good step coverage, and good process uniformity.

Abstract: A method and apparatus for determining a format for displaying information in a display area coupled to a computer system, the format being based on the size of the display area and the amount of information to display. As a user continues to enter information in the display area, software program instructions update the format of the information when the amount of information to display changes. This includes reducing the size of the font as additional information is entered and enlarging the size of the font when enough information is deleted to create available space. The font type and/or the font size may be changed to allow the information to fit within the available display area. The size of the text may be reduced to a minimum level and, and as more information is entered, the display is scrolled so the user may view the most recently entered data. A scale also be determined to reduce or enlarge graphics information so that it fits within the available display area.

Abstract: A low profile high density rack mountable enclosure with superior cooling and highly accessible re-configurable components is disclosed. One embodiment of the present invention discloses a computer system comprising a chassis for holding a plurality of computer components, a CPU having a heatsink mounted thereon, wherein the CPU is mounted in the chassis, and a first blower having an inlet for receiving air and an outlet for expelling air, wherein the first blower is mounted in the chassis proximate to the CPU. Another embodiment of the present invention discloses a retention clip for use in a computer system, the retention clip comprising a base portion having at least one tab, and a flange portion having at least one mounting hole, wherein the flange portion is connected to the base portion, and wherein the flange portion makes an angle with the base portion.

Abstract: An apparatus for electroplating a wafer surface includes a cup having a central aperture defined by an inner perimeter, a compliant seal adjacent the inner perimeter, contacts adjacent the compliant seal and a cone attached to a rotatable spindle. The compliant seal forms a seal with the perimeter region of the wafer surface preventing plating solution from contaminating the wafer edge, wafer backside and the contacts. As a further measure to prevent contamination, the region behind the compliant seal is pressurized. By rotating the wafer during electroplating, bubble entrapment on the wafer surface is prevented. Further, the contacts can be arranged into banks of contacts and the resistivity between banks can be tested to detect poor electrical connections between the contacts and the wafer surface.

Abstract: A system includes a modem which receives a burst of a time division multiple access (TDMA) signal. A burst mode controller, connected to the modem, is operable to detect a unique word in the burst. If the unique word is not detected, the burst mode controller loads a predetermined bit pattern into a channel identifier field of the burst. The predetermined bit pattern indicates that a payload field of the burst contains voice data.

Abstract: A host signal processing (HSP) modem or transceiver includes a transmit buffer and a receive buffer. The transmit buffer stores multiple blocks of information representing a transmit signal, and the receive buffer includes available space for multiple blocks of information representing a receive signal. Each block of information corresponds to its respective signal for an associated period that spans the time between consecutive interrupts for the HSP modem. When the host computer fails to service one or more interrupts, the hardware portion of the HSP modem uses the reserve of information from the transmit buffer to generate the transmit signal and stores one or more blocks of information representing the receive signal in the receive buffer. Accordingly, the HSP mode maintains the connection and data throughput even when the host computer misses interrupts.

Abstract: A system includes a unique word correlator module which correlates a unique word field in a burst of a time division multiple access (TDMA) signal against a predefined marker sequence. Automatic timing control circuitry is coupled to the unique word correlator module. The automatic timing control circuitry derives a number of errors that are allowable during correlation of the unique word field.

Abstract: A semiconductor rectifier includes a substrate of a first conductivity type; a current path layer of the first conductivity type formed near the surface of the substrate; a current block layer of a second conductivity type laterally enclosing the current path layer and extending to a depth deeper than the current path layer; and first and second metal layers formed respectively contacting upper and lower surfaces of the substrate. The current path layer has an impurity concentration higher than that of the substrate, and the current block layer has an impurity concentration higher than that of the current path layer. The current path layer is small enough for the portion below the current path layer to be completely blocked by the depletion region formed around the current block layer when a reverse bias or no is applied to the rectifier.

Abstract: A system and method are provided for selectively warming a printhead in response to a relatively sudden change in one or more operating conditions of a printer. These operating conditions may include, for example, duty cycle, print density, print speed, and the like, which can be empirically detected, calculated, or predicted. Because sudden changes in printing conditions generally do not occur frequently, the printhead will not be warmed at all for much of its operating time. This reduces dramatic fluctuations in drop volume, to prevent thermal banding, while not maintaining the printhead at an undesirably high temperature.

Abstract: In accordance with this invention, a data capture circuit of a data receiver captures data from a data stream of a data transmitter operating at a different phase or frequency from the system clock of the data receiver. In one embodiment, the data receiver determines the number of clock periods of a clock signal in a data period of the data stream. Specifically, a signal detection circuit receives a signal having a periodic and distinctive feature. The period of the periodic and distinctive feature is related to the data period by a fixed scaling factor. A counter counts the number of clock periods of the clock signal between a first occurrence of the periodic and distinctive feature and a second occurrence of the periodic and distinctive feature. A multiplier/divider circuit divides or multiples the content of the first counter by the scaling factor to determine the integer clock period count. The results of the multiply or divide is stored in a count register.