Abstract: A structured logic array is divided into hierarchical levels. At a highest level (the chip level), blocks are interconnected by a system of chip busses. A block interface couples each block to the chip bus system to allow the blocks to communicate with each other. At a lower level, each block includes sectors, each sector being coupled to a block bus system by a sector interface. The block bus system interconnects the sectors in each block to allow the sectors to communicate with each other. The block bus system is also coupled to the block interface to allow signals to be transferred between the block bus system and the chip bus system. At a lowest level, each sector includes a plurality of logic elements. The logic elements are interconnected by a sector bus system. The sector bus system is coupled to the sector interface to allow for the transfer of signals between the sector bus system and the block bus system.

Abstract: A method and system are disclosed wherein error detection codes are used for detecting and handling hardware errors in a memory table. Before each address and associated data are entered into the memory table, an error detection code is generated for both the address and the data. The address, data, and corresponding error codes are stored in the same entry line in the memory table. When the table receives an input address from a CPU, the input address is compared to all of the addresses stored within the memory table. If any stored address matches the input address, the matched address is outputted along with its associated data and its corresponding error codes. The matched address and its associated data are each processed with its corresponding error code to determine whether the outputted address and data are identical to the address and data used to generate the error codes.