Abstract: An electronic game system includes a game console, which accepts a game cartridge and runs the games stored therein, and a wireless controller for controlling actions in the game. The wireless controller includes a radio frequency transmitter for sending control signals to the console, and the console includes a receiver for receiving the control signals from the controller. Because the controller uses radio frequency signals instead of infrared signals to send information to the console, the controller may be operated at a large distance from the console. Thus, the game system of the invention may be used in long range applications wherein the console and the controller need to be separated by a relatively large distance.

Abstract: A method and apparatus are disclosed for detecting and correcting errors in the data stored within the entries of a memory table. Each time data is entered into the memory table, an error code generator generates a corresponding error code using the data. This error code is stored in the memory table along with the corresponding data. When an entry in the memory table is read out, an error detector receives the outputted data and its corresponding error code and processes the data and the error code to determine whether the outputted data contains any errors. If the outputted data contains any errors, the outputted data and error code are sent to an error correction unit. In response, the correction unit attempts to find single and double bit errors in the data by way of a compact and efficient computer program. If either a single or double bit error is found, the error correction unit corrects the error or errors to derive a set of corrected data.

Abstract: A memory is tested by subjecting the memory to three phases of testing. In the first phase, a first address in the memory is initialized by writing an initial set of data to the address. Then data is read from the address just written to and this data is modified to produce a set of modified data. The modified data is then written to another address in the memory. The steps of reading, modifying, and writing modified data back to the memory are repeated until all addresses in the memory have been written to. Thereafter, the data values stored in the memory are compared to a reference list of data values to determine whether the memory contains a detect. In phase two, the steps of phase one are repeated except that the first address in the memory is initialized by writing a set of data which is the complement of the initial set of data used in phase one. Phase two, in effect, complements the contents of each address in the memory to ensure that each cell in the memory is written with both a 0 and a 1.

Abstract: An original signal, different portions of which are captured by two or more different receivers, is reconstructed from the outputs of the various receivers. In a first embodiment, signal reconstruction is achieved by first converting the analog receiver outputs into digital signals and then shifting the frequency of at least one of the digital signals such that a frequency difference is introduced between at least two of the digital signals. Thereafter, each digital signal is processed through a corresponding filter (38, 40) to derive filtered signals. These filtered signals are combined to derive a primary output signal which is a representation of the original signal. After the primary output signal is derived, it is passed on to an error determiner (44) where an error component is computed. This error component is used to adjust the parameters of the filters (38, 40) in such a manner as to reduce the error component.

Abstract: A self-supporting convex cover for spacecraft hardware is described. In the preferred embodiment, the cover is made of a laminated material. Strips of material are inserted into the laminate in a channel shape, such that sufficiently rigid box beam structures are formed in a pattern to hold the convex shape. Ribs of foam may be placed between a layer of the laminate and the strips of material to provide the channel shape. The cover is attached to the spacecraft hardware by one or more drawstrings which are laced through the perimeter of the cover. With appropriate materials, the resulting assembly is light, inexpensive, easy to assemble, and transparent to radio frequencies, yet sturdy enough to maintain its shape during launch.

Abstract: A system for pipelining bus requests includes a bus, at least one node coupled to the bus, and a bus coordinator coupled to the node. The node uses a single bus request signal to both request control of the bus from the bus coordinator, and to retain control of the bus. In response to an asserted bus request signal from the node, the coordinator sends an asserted bus grant signal to the node to grant the node control of the bus. This bus grant signal tracks the bus request signal so that as long as the bus request signal remains asserted, the bus grant signal also is asserted. To allow for pipelining, the bus coordinator maintains the bus grant signal in an asserted state for at least one clock cycle after the bus request is deasserted. By holding the bus grant signal in the asserted state for one extra cycle, the coordinator gives the node time to deassert and then to reassert the bus request signal before the bus grant signal changes state.

Abstract: A memory is tested by subjecting the memory to three phases of testing. In the first phase, a first address in the memory is initialized by writing an initial set of data to the address. Then data is read from the address just written to and this data is modified to produce a set of modified data. The modified data is then written to another address in the memory. The steps of reading, modifying, and writing modified data back to the memory are repeated until all addresses in the memory have been written to. Thereafter, the data values stored in the memory are compared to a reference list of data values to determine whether the memory contains a defect. In phase two, the steps of phase one are repeated except that the first address in the memory is initialized by writing a set of data which is the complement of the initial set of data used in phase one. Phase two, in effect, complements the contents of each address in the memory to ensure that each cell in the memory is written with both a 0 and a 1.

Abstract: A high performance shared-bus signal detection mechanism comprises a plurality of access event registers, an address comparator, an event masking component, and a local processor access detector. The comparator component couples to a bus providing access to a shared memory address space. The bus can be used by a single processor or shared by a plurality of processors. A processor loads the address event registers with address base and extent values and type of access notification desired. As addresses and access-type signals appear on the bus, the comparator simultaneously compares the bus information to access event register information to determine if the bus access meets access event register criteria. When matches occur, the comparator emits an appropriate signal to an event masking component. The local processor also loads the event masking component to selectively mask off unwanted event notifications as well as those performed by itself.

Abstract: The provision of power to a peripheral of a computer system is controlled by first receiving input signals from an input source, such as a keyboard, mouse, printer port, or an occupancy sensor. The input signals are then processed to determine whether power should be provided to the peripheral, and if so, an activation signal is generated. In response to this activation signal, the peripheral is connected to an external power source, thereby turning the peripheral on. Thereafter, the input signals continue to be processed to determine whether power should be disconnected from the peripheral, and if so, a deactivation signal is generated. The peripheral is disconnected from the power source in response to the deactivation signal to turn the peripheral off. An apparatus for carrying out the method described above comprises an input port for receiving the input signals, a processor the processing the input signals, and a connection circuit for selectively connecting the peripheral to a power source.

Abstract: A dynamic random access memory (DRAM) circuit operates in burst mode when a row address strobe (RAS) signal is applied while an output enable/burst enable signal is also applied thereto. During burst mode, a column address strobe (CAS) signal is toggled to access digital data from sequential column addresses within a given row.

Abstract: A system and a method are described for optimizing the sequencing and time requirements for compiling large sets of source code residing in multiple hierarchical file directories using an abstracted logical description of the hierarchical file relations existing between directories. The system consists of a logic processor working in concert with input and output file registers, a match register, and an abstracted tree register for the purpose of creating a identifying, comparing, and sequencing file names in a final description of the global directory. The method iteratively identifies the primary input files and the intermediate input files for a given output file for each of a series of directories, inverts the casual relationship between the output file and its intermediary input files, and accumulates and stores these relationships in a sequential manner for subsequent use.

Abstract: A system and method are described for decreasing the synthesis time required for realizing digital circuit net lists using library logic elements. The system consists of a logic processor working in concert with a cell library register, a hierarchical cell array memory, and a match register, for the purpose of hierarchically ordering, matching and eliminating equivalencies in the canonical forms of library cells. The method includes the reduction of all library elements to their canonical forms and the hierarchical ordering of the these canonicals based on the number of nodes contained in each element. Once ordered, the canonicals are mapped by logic elements having fewer nodes, beginning with the simplest of the canonical forms. Redundantly mapped logical elements are eliminated and the resulting reduced set is stored for subsequent use.

Abstract: A method and apparatus for providing a lower frequency signal with reference to a higher frequency signal are disclosed. The apparatus of the invention comprises an oscillating signal generator, an integer logical divider, and a signal combiner. The signal generator receives an input voltage and, in response thereto, generates a first output oscillating signal and a second output oscillating signal, both having a first frequency. The two oscillating signals are separated by a ninety-degree phase shift. The integer logical divider receives the two oscillating signals and provides two output divided signals in response. The first divided signal is representative of the first oscillating signal except that its frequency is one-third the frequency of the first oscillating signal. Likewise, the second divided signal is representative of the second oscillating signal except that its frequency is one-third that of the second oscillating signal.

Abstract: An improved circuit layout-verifying system and method operates on a plurality of polygons that are representative of an electrical node to test the proper or improper connection of each polygon to another contiguous polygon and designates for display those polygons that represent improper connections between known or identified reference points on the node. Traversals along a sequence of contiguous polygons between known reference points on the same electrical node are designated as proper connections or successes, and traversals along a sequence of contiguous polygon between reference points associated with different electrical nodes are designated as improper connections or failures at least along a portion of the sequence. Data from all traversals of all polygons from all known reference points is then analyzed to remove unambiguous sequences of polygons for the improperly connected electrical nodes.

Abstract: A method and apparatus for determining the quality of a colloidal suspension. According to the method of the present invention, an oscillating input electrical signal is applied simultaneously to a sample of the colloidal suspension to be tested and to a reference solution. The reference solution is substantially identical to the colloidal suspension except that the colloidal particles have been removed. The input signal causes charge particles and molecules within both substances to move, thereby, giving rise to electrical currents. Thus, a test current is extracted from the colloidal suspension and a reference current is extracted from the reference solution. Thereafter, a differential output current is derived by substracting the reference current from the test current. The peak-to-peak magnitude of the differential output current is measured, and the phase of the output current is compared to the phase of the input signal to determine the difference in phase between the two signals.

Abstract: The method and apparatus for efficiently storing or transmitting related sets of data such as X, Y coordinate data determines the resolution of a display device and the transmission limitations of a communication channel to the display device and encodes a selected portion of the bitmap for display with associated offsets and additional information as a complex number according to a variable-radix polynomial, where the number is segmented into selected bytes for transmission within the operating limitations of the communication channel for decoding and restoration of offsets by the display device.