Abstract: A method and system are described to group logic terms at a higher level of abstraction than that found using standard cells to implement the logic functions using a reduced number of transistors, and to reduce the total number of unique geometry patterns needed to create the integrated circuit implementation. By grouping the logic functions in terms of a larger number of literals (logic variable inputs), the functions can be implemented in terms of a number of transistors that is often less and no more than equal to that which is required for implementing the same function with a number of logic primitives, or simpler standard logic cells. The optimized transistor level designs are further optimized and physically constructed to reduce the total number of unique geometry patterns required to implement the integrated circuit.

Abstract: A system for generating processor hardware supports a language for significant extensions to the processor instruction set, where the designer specifies only the semantics of the new instructions and the system generates other logic. The extension language provides for the addition of processor state, including register files, and instructions that operate on that state. The language also provides for new data types to be added to the compiler to represent the state added. It allows separate specification of reference semantics and instruction implementation, and uses this to automate design verification. In addition, the system generates formatted instruction set documentation from the language specification.

Abstract: A method of generating a mask for use in an imaging process pattern. The method includes the steps of: (a) obtaining a desired target pattern having a plurality of features to be imaged on a substrate; (b) simulating a wafer image utilizing the target pattern and process parameters associated with a defined process; (c) defining at least one feature category; (d) identifying features in the target pattern that correspond to the at least one feature category, and recording an error value for each feature identified as corresponding to the at least one feature category; and (e) generating a statistical summary which indicates the error value for each feature identified as corresponding to the at least one feature category.

Abstract: A method of calibrating a simulation model of a photolithography process. The method includes the steps of defining a set of input data; defining a simulation model having model parameters which affect the simulation result produced by the simulation model; performing a first stage calibration process in which the model parameters and alignment parameters are adjusted such that the simulation result is within a first predefined error tolerance; and performing a second stage calibration process in which the alignment parameters are fixed and the model parameters are adjusted such that the simulation result is within a second predefined error tolerance.

Abstract: A system, method, and apparatus for providing an embedded controller in a modem device for enabling data communication between different networks. Management and control capabilities for a gateway function are embedded into a communication controller of the modem device so as to enable direct connection between wired and wireless devices while eliminating a separate gateway controller. A single controller in the modem device, wired or wireless, manages its own designated communication functions and data exchange between the two different networks.

Abstract: A method and an apparatus for detecting, locating, and quantifying contamination in a fluid flow system like a pipe or duct. This characterization technique uses a conservative and one or more interactive tracers that are injected into the fluid flow system and then monitored at another location in the system. Detection, location, and quantification are accomplished by analysis of the characteristic features of measured curves of tracer concentration.

Abstract: A system and method for enabling remote management of data of devices using wireless communications. The system and method provides direct access to devices such as sensors from wireless devices having an integrated wireless transceiver and controller that are user programmable such a separate remote host controller is not required for managing the sensors. In one embodiment, a broadcast mode is provided wherein the wireless devices transmits a response for its corresponding sensors according to a predetermined sequence during a predetermined time slot according to a predetermined sequence.

Abstract: A system for adding advanced instructions to a microprocessor includes a language for formally capturing the new instructions and a method for generating hardware implementations and software tools for the extended processors. The extension language provides for additions of VLIW instructions, complex load/store instructions, more powerful description styles using functions, more powerful register operands, and a new set of built-in modules. The method is capable of generating fully-pipelined micro-architectural implementations for the new instructions in the form of synthesizable HDL descriptions which can be processed by standard CAD tools. The method is also capable of generating software components for extending software development tools for the microprocessor with new instructions.

Abstract: An apparatus, method, and computer-readable media that provide fast and accurate prediction of the hardware cost of logic to extend a processor. Aspects of the invention enable designers to explore instruction set alternatives at the architectural level without completing a lengthy implementation flow. Embodiments may use existing standard cell libraries and EDA tools to obtain the cost of parameterized building blocks, to build components of a microprocessor such as instruction decoder, register files, and data path execution units. The cost of an application specific microprocessor is derived from the cost of each of its structural components.

Abstract: A method and apparatus provides for accurately synchronizing a plurality of sensors, as well as for providing accurate timing information (e.g. timing metadata) associated with the synchronized data capture. According to one aspect of the invention, an apparatus includes a synchronization circuit that stores a counter having a value corresponding to the delay characteristics of an associated sensor. The counter is used to provide a synchronization pulse to the associated sensor which is offset from a desired synchronization time by an amount that will compensate for the delay characteristics. In one example, one counter is provided for each associated sensor, allowing a high degree of accuracy in synchronization among a plurality of sensors. According to another aspect of the invention, the synchronization pulses are locked onto and derived from a pulse received from a GPS receiver.

Abstract: A method of constructing a dual metal gate CMOS structure that uses an ultra thin aluminum nitride (AINx) buffer layer between the metal gate and gate dielectric during processing for preventing the gate dielectric from being exposed in the metal etching process. After the unwanted gate metal is etched away, the CMOS structure is annealed. During the annealing, the buffer layer is completely consumed through reaction with the metal gate and a new metal alloy is formed, resulting in only a minimal increase in the equivalent oxide thickness. The buffer layer and gate metals play a key role in determining the work functions of the metal/dielectric interface, since the work functions of the original gate metals are modified as a result of the annealing process.

Abstract: A processor method and apparatus that allows for the overlapped execution of multiple iterations of a loop while allowing the compiler to include only a single copy of the loop body in the code while automatically managing which iterations are active. Since the prologue and epilogue are implicitly created and maintained within the hardware in the invention, a significant reduction in code size can be achieved compared to software-only modulo scheduling. Furthermore, loops with iteration counts less than the number of concurrent iterations present in the kernel are also automatically handled. This hardware enhanced scheme achieves the same performance as the fully-specified standard method. Furthermore, the hardware reduces the power requirement as the entire fetch unit can be deactivated for a portion of the loop's execution.

Abstract: The present invention relates to micro-electro-mechanical systems (MEMS). The present invention relates to a design feature that allows lower actuation voltage for electrostatically actuated structures (i.e., switches or mirrors). The present invention further relates to a method for fabricating such a design that allows lower actuation voltage.

Abstract: The invention provides a computer implemented method, system, and computer program device for web-enabling a device. An application for remote monitoring and controlling capabilities may be automatically generated, to enable easy development of embedded applications. The application may be loaded onto a device that is to be web-enabled. The application on the device may offer interaction capabilities from standard browsers. A software modeling tool, e.g., a UML-based tool, supplies mechanisms for annotating software elements, and generating and/or customizing code and/or the user interface and/or device elements to be exposed to the web, thereby providing a fast-prototyping and collaborative environment for research and development teams. The web-enabled device may store a copy of the user interface locally. Preferably, the web-enabled device provides real-time updates of device information while connected to the remote user.

Abstract: An advanced data structure allows lookup based upon the most significant 16 bits and the following variable number of K bits of the IP destination address. This 16/K scheme requires less than 2 MB memory to store the whole routing tables of present day backbone routers. A 16/Kc version utilizes bitmaps to compress the table to less than 0.5 MB. For the 16/K data structure each route lookup requires at most 2 memory accesses while the 16/Kc requires at most 3 memory accesses. By configuring the processor properly and developing a few customized instructions to accelerate route lookup, one can achieve 85 million lookups per second (MLPS) in the typical case with the processor running at 200 MHz. Further, the lookup method can be implemented using pipelining techniques to perform three lookups for three incoming packets simultaneously. Using such techniques, 100 MLPS performance can be achieved.

Abstract: A novel solution for fast packet classification includes a novel data structure to store classifier rules which enables fast packet classification, which structure employs bitmaps for each field of the incoming packet for which classification is desired. A fast packet classification algorithm using the novel data structure allows the matching rule with the highest priority to be quickly obtained. A novel rule update algorithm allows new classifier rules to be added into the data structure incrementally. In one practical implementation of a classification engine employing the structures and algorithms of the present invention, a configurable processor with customized instructions is used to accelerate packet classification.

Abstract: A fast and accurate non-contacting angle sensor. According to one aspect of the described sensor and method of operation thereof, the angular orientation of an inner payload relative to an outer structure is monitored with a 2 axis optical angle sensor for azimuth and elevation angles. The sensor operates on the same principle as an autocollimator, thus it measures both azimuth and elevation angles simultaneously. The angle sensor measurements are highly accurate in the angles of interest, while having low sensitivity to translation in three axes and low sensitivity to roll angle between the inner payload and the outer structure.

Abstract: A processor can achieve high code density while allowing higher performance than existing architectures, particularly for Digital Signal Processing (DSP) applications. In accordance with one aspect, the processor supports three possible instruction sizes while maintaining the simplicity of programming and allowing efficient physical implementation. Most of the application code can be encoded using two sets of narrow size instructions to achieve high code density. Adding a third (and larger, i.e. VLIW) instruction size allows the architecture to encode multiple operations per instruction for the performance critical section of the code. Further, each operation of the VLIW format instruction can optionally be a SIMD operation that operates upon vector data. A scheme for the optimal utilization (highest achievable performance for the given amount of hardware) of multiply-accumulate (MAC) hardware is also provided.

Abstract: An apparatus and method for ion generation are adapted such that an ionization process is controlled temporally, to first initiate, then to halt the breakdown of the gas before a destructive plasma or glow is formed. This method controls the release of energy to the gas in such a manner as to create ions but prevent the heating of the gas. The primary advantages of this ion generation mechanism are its simplicity, efficiency and its ability to create ions at ambient temperature and pressure.