Abstract: Output driver stages and operation modes for selectively disabling device outputs are adapted for use in integrated circuit devices and in the testing of such integrated circuit devices. A device output is disabled by disabling its associated output driver. A first control signal is generated that is indicative of whether an output driver should be responsive to a second control signal or disabled regardless of the second control signal. The first control signal may be provided directly to one or more output drivers. Alternatively, the first control signal may be combined with the second control signal. The first control signal may be common to all coupled output drivers or a separate first control signal may be provided for each output driver. Selective disabling of output drivers can be used to force a device time-out during testing. Selective disabling of output drivers can also be used to reduce device power requirements.

Abstract: A method for controlling gain in a network is provided. The method includes receiving signals for transmission over a network and adjusting the level of the received signals. The method further includes inserting an additional signal indicative of the level adjustment and transmitting the signals and the additional signal over the network. The method also includes extracting the additional signal after transmission over the network and compensating for the level adjustment based on the extracted signal.

Abstract: Memory devices including blocks of memory cells arranged in columns, with each column of memory cells coupled to a main bit line, are organized for high-speed access and tight packing. Such memory devices include sector bit lines having multiple main bit lines selectively coupled to each sector bit line, with each sector bit line extending to main bit lines in each memory block of a memory sector. Sector bit lines are coupled to sensing devices and the output of each sensing device is selectively coupled to a global bit line, with each global bit line selectively coupled to more than one sensing device. The global bit lines are multiplexed and input to helper flip-flops for output to the data output register of the memory device. Various embodiments include non-volatile, and, particularly, synchronous non-volatile memory devices having multiple banks containing multiple sectors of such memory blocks.

Abstract: Method for forming at least a portion of a top electrode of a container capacitor and at least a portion of a contact plug in one deposition are described. In one embodiment, the top electrode is formed interior to a bottom electrode of the container capacitor. In another embodiment, the top electrode is formed interior to, and exterior and below a portion of the bottom electrode of the container capacitor. The method of forming a top electrode of a container capacitor and a contact plug with a same deposition is particularly well-suited for high-density memory array formation.

Abstract: A method of forming an extraction grid for field emitter tip structures is described. A conductive layer is deposited over an insulative layer formed over the field emitter tip structures. The conductive layer is milled using ion milling. Owing to topographical differences along an exposed surface of the conductive layer, ions strike the exposed surface at various angles of incidence. As etch rate from ion milling is dependent at least in part upon angle of incidence, a selectivity based on varying topography of the exposed surface (“topographic selectivity”) results in non-uniform removal of material thereof. In particular, portions of the conductive layer in near proximity to the field emitter tip structures are removed faster than portions of the conductive layer between emitter tip structures. Thus, portions of the insulative layer in near proximity to the field emitter tip structures may be exposed while leaving intervening portions of the conductive layer for forming the extraction grid.

Abstract: Disclosed is a container capacitor structure and method of constructing it. An etch mask and etch are used to expose portions of an exterior surface of electrode (“bottom electrodes”) of the container capacitor structure. The etch provides a recess between proximal pairs of container capacitor structures which recess is available for forming additional capacitance. Accordingly, a capacitor dielectric and a top electrode are formed on and adjacent to, respectively, both an interior surface and portions of the exterior surface of the first electrode. Advantageously, surface area common to both the first electrode and second electrodes is increased over using only the interior surface, which provides additional capacitance without a decrease in spacing for clearing portions of the capacitor dielectric and the second electrode away from a contact hole location.

Abstract: A read reference scheme that uses current load matching on a reference word line path. In one embodiment, a flash memory device comprises a word line, a reference word line and a reference load circuit. The word line is coupled to a control gate of a memory cell. The reference word line is coupled to a control gate of a reference memory cell. In addition, the reference load circuit is coupled to the reference word line to approximately match a current load on the word line so a voltage level on the reference word line will be approximately equally to a voltage level on the word line during a read operation.

Abstract: A non-volatile memory device includes an array of erasable blocks of non-volatile memory cells. At least one of the blocks has at least one redundant column. A block register is associated with each erasable block. Each block register stores data that indicates when its associated erasable block is fully erased. A control circuit is used to perform an erase verification on each erasable block and provide data to the block registers based on an outcome of the erase verification. The control circuit performs the erase verification of the at least one redundant column in conjunction with the erasable block where the at least one redundant column resides.

Abstract: Methods and apparatus for decoding an externally-applied address in a synchronous memory device are arranged to decode a first portion of the address during a setup time and to decode a second portion of the address following the setup time. The first portion of the address may be indicative of a bank address of a multiple-bank memory device. The second portion of the address may be indicative of row and column addresses within a bank of the multiple-bank memory device. Decoding of the first portion of the address is performed by an address input buffer stage having a decoder interposed between the input buffers and the address latches, such that the decoder generally replaces a delay stage of a typical input buffer stage. As such, the first portion of the address is decoded during a setup time. By decoding the first portion of the address during a setup time, it is available to direct the second portion of the address to a proper decoder substantially without delay.

Abstract: A known clock frequency is divided into at least two phases, and the rising and the falling edges of each of the divided signals are counted. The sum total of edges in a given time period is compared to a stored sum of edges during an earlier time period of the same duration. Adjustment to the local clock is made if sufficient differences are detected.