Abstract: The present invention provides a C-V method for measuring an effective channel length in a device, which can simultaneously measure a gate-to-drain overlap length and a gate etch bias length in the device. In the present method, the measured length of the gate by using the present method has a deviation below 5% compared with the real gate length form SEM. Furthermore, the calculating method of the present invention only uses simple simultaneous equations, which can be measured by a man or a mechanism. As the layout rule shrunk, the present method provides a simple way to measure those parameters, which have become more and more important in the device.

Abstract: A method for suppressing boron penetrating the gate dielectric layer by pulsed nitrogen plasma doping. A pulsed nitrogen plasma doping process is utilized to dope nitrogen ions into the surface layer in the channel region of the semiconductor substrate. A thermal oxidation step is then performed to form a gate dielectric layer commixed with oxide and oxynitride over the channel region of the semiconductor substrate to avoid boron penetration effect accruing while a boron doped polysilicon layer is subsequently formed on the gate dielectric layer.

Abstract: A digital clock throttling device, for gating a clock signal of a circuit, at least includes an accumulator and a gating circuit. The accumulator responsive to a throttling value generates a first output signal. The first output signal is divided into a throttling signal with a most significant bit and a feedback signal with rest bits of the first output signal except for the most significant bit. The feedback signal is sent to the accumulator back for accumulating to the throttling value as the first output signal. The gating circuit coupling with the accumulator responsive to the throttling signal and clock signal gates out some clock cycles of the clock signal, thereby providing a gated clock signal in an adjusted frequency.

Abstract: A pad oxide layer is formed on a substrate, wherein the thickness of the pad oxide layer is about greater than 250 Å. The alignment photo-resist layer is selectively patterned by a conventional lithography method to define the N-well region. The pad oxide layer is partially etched by using etch method with the alignment photo-resist pattern as a mask until the thickness of the pad oxide layer is about 100 Å to form an alignment mark. The N-type ion-implant is performed by the alignment photo-resist pattern as a mask to form an N-doped region in the substrate. Then, the alignment photo-resist pattern is removed. The P-well photo-resist is defined and formed on the pad oxide layer, then performing a P-type ion-implant through the pad oxide layer into the substrate by means of the P-well photo-resist as a mask to form a P-doped region. Then remove the P-well photo-resist and proceed with the drive-in process to form the N-well region and P-well region.