Abstract: A method of fabricating a memory device and a logic device on the same chip is described, wherein the memory device has a first gate on a first region of the chip, and wherein the logic device has a second gate with a sidewall on a second region of the chip. A conductive layer and a first suicide layer are sequentially formed over the first and the second regions of the chip. Over the first region of the chip, the first silicide layer and the conductive layer are patterned to form the first gate. Ions are first implanted into the first region of the chip, by using the first gate as a mask, to form a first doped region. A dielectric layer is formed to cap the first gate, the first doped region and the first region of the chip. The first silicide layer over the second region of the chip is removed. Over the second region of the chip, the conductive layer is patterned to form the second gate.

Abstract: The present invention relates to a cooling system of a furnace, more particularly, to a multi-cycle cooling system, located by the furnace door. The probability of pollution by particles can be decreased and the lifetime of the furnace devices can be extended by using different liquid and gas cycles, cooling the different steps the semiconductor processes in the furnace.

Abstract: A method for forming thin film transistor with lateral crystallization. The method at least includes the following steps. First of all, an insulation substrate is provided. Then, an amorphous silicon layer is provided on the insulation substrate. The seeds are formed by annealing a portion of the amorphous silicon layer by excimer laser system, and the lateral-growth grain is formed by using the seeds to grow laterally by annealing the amorphous silicon layer, wherein the amorphous silicon layer defines an active region. Then, sequentially a dielectric layer and a polysilicon layer is deposited on the active region, wherein the dielectric layer and the polysilicon layer are gate electrodes, a gate is defined on the substrate, and the polysilicon layer is formed by etching. Next, source and drain regions are formed by implanting numerous ions into amorphous silicon layer by using the gate electrode as a mask.

Abstract: Structures for reducing relative stress between HDP layer and passivation layer are proposed by the invention, where the HDP layer is formed by high density plasma and the passivation layer is a conventional passivation layer. The invention provides some structures that can be divided into two categories: one, a low stress passivation layer is directly formed on a HDP layer; another, a low stress layer is formed between passivation layer and HDP layer to reduce relative layer that between any two adjacent layers. Therefore, it is crystal-clear that possible structures of the invention comprise following varieties: First, a low stress passivation layer is located between a passivation layer and a HDP layer. Second, a lower stress passivation layer directly locates on a HDP layer. Third, a low stress layer is formed between a passivation layer and a HDP layer.

Abstract: A substrate is provided. A first dielectric is formed over the substrate, and an etching stop layer and a second dielectric are formed in turn on the first dielectric by deposition. An anti-reflection layer is formed over the second dielectric. Then, a photo-resist layer is formed and defined over the anti-reflection layer. A gap-filling material is filled on the second dielectric and into the via hole. Subsequently, the gap-filling material is etched back and is turned on the end point and the long over etch is applied to make sure the photo-resist thickness is below middle stop layer. If the first dielectric reacts with the photo-resist plug in the via hole, the bottom anti-reflection coating or thin oxide are used as a barrier before the trench photo-resist is patterned. If the first dielectric does not react with the photo-resist plug in the via hole, the trench photo-resist is patterned directly. Then, the trench etch is performed.

Abstract: A membrane probe card is provided. The membrane probe card includes a pressure mechanism having an upper-housing and a support block. The support block has a spring system for providing a distance of travel to the support block. A printed circuit board is coupled to the pressure mechanism for providing electrical connection to a test apparatus. A membrane assembly is coupled to the pads on a wafer for providing electric connection to the printed circuit board. The membrane assembly is a replaceable and modularized component for application to integrated circuits with various layouts and dimensions.

Abstract: A memory array architecture includes a plurality of memory cells formed into rows and columns. A plurality of bit lines is connected to the memory cells through select transistors. By disposing adjacent bit lines into different metal layers or alternatively interlocating adjacent bit lines, the coupling effect between bit lines can be effectively reduced, and thus can improve reading speed of memory while performing read operation.

Abstract: A substrate is provided. A first dielectric layer is formed over the substrate by deposition. Etching stop layer and a second dielectric layer are formed in turn over the first dielectric. Next, the second dielectric layer is dealt with Lewis acid. Then, a first photoresist layer is defined and formed over the second dielectric layer. And then dry etching is carried out by means of the first photoresist layer as the mask to form a via hole. The surface of the second dielectric layer and the via hole are treated with Lewis acid. Subsequently, the second photoresist layer is defined and formed on the second dielectric layer. Dry etching is proceed, and etching stop layer is as a etching terminal point to remove exposed partial surface of the second dielectric layer so as to form a trench having larger horizontal size than the via hole. Subsequently, the second photoresist layer is removed to form the opening of the damascene.

Abstract: A dynamic-capacity-demand-forecast system in the manufacture of semiconductor integrated circuits includes several steps. N types of products and m types of processing steps are in a processing line. The turn ratio of each products at each stages on a specified working day is calculated and the work-in-process (WIP) of every product at each stages on the same day is determined. According to these two numbers, the WIP on the next working day can be calculated, and then the move on the next working day is determined. Using this formula, the move of each product at each stage in future is obtained. Also, the summation the moves of all products at all stages on a working day are equal to, the capacity demand of the processing line on that day. The quantity of the throughput of the wafers may thus be determined and the supervisor can decide how to vary the parameters of the processing line.

Abstract: The present invention proposes a die seal ring. The provided die seal ring is formed on a substrate and is used to encompass a die by locating between the die and adjacent scribe lines. Moreover, the provided die seal ring comprises a plurality of dielectric layers and a plurality of metal structures, wherein any metal structure is not overlapped with other metal structures. Moreover, dielectric layers are located on the substrate in sequence, and each metal structure is stacked by one metal ring and one metal plug. In addition, any metal ring is located on a dielectric layer and is covered by another dielectric layer, and metal rings of different metal structures are located on different dielectric layers. Further, any metal plug is located in the dielectric layers and is used to connect the metal ring to the substrate. Of course, if the aspect ratio of any metal plug is too large to be properly formed, an appendant metal ring is used to reduce the aspect ration of the metal plug.

Abstract: A phase shift mask for photolithography used in fabricating integrated circuits is disclosed. The mask comprises a transparent plate and a first opaque film formed on said transparent plate, which has a first pattern defining a main feature region. The first pattern is then imaged onto a photoresist layer coated on a wafer for the integrated circuits. The present invention further comprises at least one phase shift region formed on said transparent plate to correspond to an active region of the wafer, in which the phase shift region is used to improve optical scattering effect of the first pattern through the active region while performing the photolithography. Moreover, the present invention comprises at least one second opaque film formed on said transparent plate to correspond to a non-active region of the wafer, in which each has at least one second pattern used to improve optical scattering effect of the first pattern through the non-active region while performing the photolithography.

Abstract: A method for transmitting data in a wireless modem network including a plurality of wireless modems is disclosed herein. The method mentioned above includes the following steps. First, classify the plurality of wireless modems into a plurality of groups. Next, select a plurality of group masters. Every group master is selected from the wireless modems enclosed by the group enclosing the group master. Subsequently, when a wireless modem wants to broadcast a data, if the wireless modem is not a group master, then the wireless modem transmits the data to the group master that dominates the wireless modem. Next, begin at the group master mentioned above; check whether any of the plurality of the group masters has not received the data. If there is any group master having not received the data, then any of the group masters that has received the data transmits the data to the farthest group master that has not received the data.

Abstract: A method and structure for testing embedded flash memory including a memory array and a logic element. A control transistor is disposed and is connected between a sense amplifier and an I/O buffer in the memory array, and a speed control pin connected to the logic element in one terminal is coupled to the gate terminal of the control transistor in the other terminal to switch the control transistor on or off. Turning off the control transistor after a test time by the speed control pin closes the channel between the sense amplifier and I/O buffer, and an output signal from the memory array to a test system connected to the logic element is detected with the test system to determine an access time of the memory array.

Abstract: Non-volatile semiconductor memory device for high-density and high-speed mass storage applications is described, in which a method for simultaneously fabricating field-oxide isolation and floating gate of non-volatile semiconductor memory device having high coupling ratio and embedded double-sides erase cathodes and a method for fabricating scalable split-gate non-volatile semiconductor memory device are disclosed. The field-oxide isolation is obtained by a special multilayer oxidation masking structure of the present invention, in which the field-doping encroachment and the bird's beak extension into the active regions of the minimum feature size can be eliminated and the smaller isolation area occupied together with the embedded double-sides erase cathodes are prepared for fabricating scalable split-gate non-volatile semiconductor memory device of the present invention.

Abstract: In present invention we provide a vertical two-transistor memory cell consisted of a MOS transistor and an ETOX cell. One of the drain or source of the MOS transistor is connected to the control gate of the ETOX cell, the other is acted as the control gate of the vertical two-transistor memory cell and is connected to a control line. And the gate of the MOS transistor is acted as the select gate of the vertical two-transistor memory cell and is connected to a word line. The drain of ETOX cell is connected to a bit line, and the source of ETOX cell is grounded. The vertical two-transistor memory cell can be programmed by channel Fowler-Nordheim tunneling of electrons which is injected from the substrate through the channel and tunnel oxide into the floating gate. Such memory cell can avoid the word line disturb by controlling the word line.

Abstract: The array includes: a plurality of pseudo spin valve (PSV) cells; a plurality of parallel bit lines, wherein a plurality of bit lines are straight lines and located under the plurality of pseudo spin valve (PSV) cells; a plurality of parallel word lines, wherein a plurality of word lines are continuous-bended lines having a first straight line, a second straight line and a third straight line. These straight lines of the word lines are orthogonal each other, wherein the first straight line and the third straight line are parallel. The first straight line and the third straight line are individually orthogonal with the direction of the bit lines. Furthermore, the second straight lines of the word lines are individually located on the pseudo spin valve (PSV) cells, and the second straight lines are parallel with the direction of the bit lines, so as to increase the magnetresistance ratio.

Abstract: The present invention provides a method for forming a poly spacer ETOX (Electron Tunnel Oxide) flash memory device with a floating gate having electric-field enhancing corners for poly to poly erase. Here, a polysilicon spacer is used as an erase gate. A floating gate having four acute angles from top view is formed, it can raise the electric field between the floating and the erase gate. The present invention can not only raise the efficiency of the erasing mechanism but also reduce the stress produced by transferred electrodes through the tunnel oxide layer in program/erase cycles and lessen the cell size with poly to poly erase.

Abstract: A wafer load/unload apparatus used to load/unload the wafer into/from the clamp ring for performing the E-Gun evaporation process is disclosed. The apparatus comprises a base, a central cylinder and a plurality of peripheral cylinders. The base has an even upper surface, and the central cylinder and the plurality of the peripheral cylinders are connected to the upper surface of the base respectively, wherein the plurality of the peripheral cylinders are located around the central cylinders. A recessed trench penetrating through sidewalls of the central cylinder is formed on a top surface of the central cylinder. The central cylinder can penetrate through a clamp ring, wherein the clamp ring is used to load a wafer for performing the E-Gun evaporating process. The spacing distances between the plurality of peripheral cylinders and the central cylinder are bigger than the width of the clamp ring.