Patents Represented by Attorney Preston Gates & Ellis LLP
  • Patent number: 7363199
    Abstract: Movement of a soft body is simulated by defining its surface as an arbitrary mesh of points connected by edges. Each point is represented as a point mass, subject to conventional laws of motion. The simulator represents forces acting on the point masses, namely skin forces connecting pairs of point masses and volumetric forces for maintaining relative positions with no net linear or rotational forces on the soft body.
    Type: Grant
    Filed: April 24, 2002
    Date of Patent: April 22, 2008
    Assignee: Telekinesys Research Limited
    Inventors: Hugh Reynolds, Andrew Bond, Andrew Bowell
  • Patent number: 7361541
    Abstract: A semiconductor light emitting device and a method to form the same are disclosed. The device has at least one porous or low density dielectric region formed in or on top of a bottom electrode, at least one top electrode on the porous or low density dielectric region, and one or more color filters placed above the top electrode, wherein the porous or low density dielectric region contains light emitting nanocrystal materials.
    Type: Grant
    Filed: July 27, 2005
    Date of Patent: April 22, 2008
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien-Chao Huang, Fu-Liang Yang
  • Patent number: 7361968
    Abstract: A method for integrally forming a metal-oxide-semiconductor (MOS) device and an electrical fuse device on a semiconductor substrate includes the following steps. An isolation structure is formed on the semiconductor substrate. A dielectric layer is deposited over the isolation structure and the semiconductor substrate. A metal layer is deposited on the dielectric layer. A polysilicon layer is deposited on the metal layer. The dielectric layer, the metal layer and the polysilicon layer are patterned into a first stack of the dielectric layer, the metal layer and the polysilicon layer on the isolation structure for functioning as the electrical fuse device, and a second stack of the dielectric layer, the metal layer and the polysilicon layer on the semiconductor substrate for functioning as a gate of the MOS device.
    Type: Grant
    Filed: March 23, 2006
    Date of Patent: April 22, 2008
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chiang-Ming Chuang, Liang-Kai Han
  • Patent number: 7362598
    Abstract: A power converter that includes a transformer, a bridge input circuit, a self-driven synchronous rectifier circuit, a gate drive circuit, and a gate drive shutdown circuit. The transformer includes a primary winding connected to the bridge input circuit, a first secondary winding, and a second secondary winding. The self-driven synchronous rectifier circuit is connected to the first secondary winding and includes a first synchronous rectifier for rectifying a voltage across the first secondary winding. The first synchronous rectifier includes a control terminal responsive to a voltage across the second secondary winding. The gate drive circuit includes a first diode connected to the control terminal of the first synchronous rectifier for introducing a dc level shift thereto.
    Type: Grant
    Filed: December 17, 2004
    Date of Patent: April 22, 2008
    Assignee: Artesyn Technologies, Inc.
    Inventors: Todd Martin Schaible, John Phillip Schmitz
  • Patent number: 7362555
    Abstract: An ESD protection circuit is implemented for a semiconductor device having a first circuit system operating with a first power supply voltage and a first complementary power supply voltage, and a second circuit system operating with a second power supply voltage and a second complementary power supply voltage. The ESD protection circuit includes a first diode having an anode coupled to the first power supply voltage and a cathode coupled to a first node connecting the first circuit system and the second circuit system for preventing a crosstalk of current between the first power supply voltage and the second complementary power supply voltage. A first MOS transistor module is coupled between the first node and the first complementary power supply for selectively creating a current path from the first node to the first complementary supply voltage for dissipating an ESD current during an ESD event.
    Type: Grant
    Filed: August 26, 2006
    Date of Patent: April 22, 2008
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chau-Neng Wu, Jian-Hsing Lee
  • Patent number: 7355849
    Abstract: The present invention relates to a chassis structure for an electronic system containing a plurality of electronic components therein. The present invention provides a composite chassis structure comprising a nonmetal mesh cover formed on one or more surfaces of the metal chassis to obtain additional thermal budget and human-friendly chassis surface.
    Type: Grant
    Filed: August 30, 2006
    Date of Patent: April 8, 2008
    Assignee: VIA Technologies, Inc. of R.O.C.
    Inventor: Shih-Chang Ku
  • Patent number: 7355704
    Abstract: A film for surface enhanced raman scattering may be utilized for chemical and biological sensing. The film includes a polymeric layer, and a metallic nanoparticle having a cross-section, the metallic nanoparticle being embedded in the polymeric layer. The polymeric layer has a thickness less than a largest straight line through the cross-section of said metallic nanoparticle. The polymeric layer is selected from a group of absorbing media and amplifying media, and the metallic nanoparticle may be gold. The metallic nanoparticle may also be a shape selected from a group of spheroids and rods.
    Type: Grant
    Filed: June 13, 2006
    Date of Patent: April 8, 2008
    Assignee: Solaris Nanosciences, Inc.
    Inventor: Nabil M. Lawandy
  • Patent number: 7354833
    Abstract: This invention provides a method for improving threshold voltage stability of at least one metal-oxide-semiconductor (MOS) device. In one embodiment of the invention, at least one well is formed on a semiconductor substrate. A gate dielectric layer is formed on the well of the semiconductor substrate. A gate conductive layer is formed on the gate dielectric layer. Ions are implanted into the well to from at least one first buried doped region beneath the gate dielectric layer, and one or more second buried doped regions beneath at least one location of the well that is earmarked for forming a lightly doped drain (LDD) region.
    Type: Grant
    Filed: June 10, 2005
    Date of Patent: April 8, 2008
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Jhon Jhy Liaw
  • Patent number: 7356434
    Abstract: This invention discloses a method of specifying pin states for a memory chip having one or more pins. In one embodiment of the invention, the pins are prioritized to obtain a pin order, wherein the pin state of a pin of a higher order dominates the pin state of a pin of a lower order. A number of possible combinations of the pin states are generated for the pins based on the pin order. The possible combinations are presented using a data presentation format. At least one pin of a higher order dominates at least one pin of a lower order when the at least one pin of a higher order is set in a predetermined pin state, such that the number of the possible combinations presented is reduced by neglecting combinations generated by the pins states of the dominated pins.
    Type: Grant
    Filed: May 12, 2005
    Date of Patent: April 8, 2008
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jeremy Wu, Yu Jen Chen, Huan An Wu, Wei-Chia Cheng
  • Patent number: 7354447
    Abstract: A disposable loading unit. The disposable loading unit includes a housing assembly, a knife assembly connected to the housing assembly, and an agent cartridge connected to the housing assembly. The agent cartridge houses a medical agent. The disposable loading unit is configured to deliver the medical agent proximate a cutting surface of the knife assembly.
    Type: Grant
    Filed: November 10, 2005
    Date of Patent: April 8, 2008
    Assignee: Ethicon Endo-Surgery, Inc.
    Inventors: Frederick E. Shelton, IV, Leslie M. Fugikawa
  • Patent number: 7352074
    Abstract: A system for producing hydrogen from water, making use of a stream of water such as a gulf stream or tidal stream, includes a number of submerged modules, each having a turbine that can be driven by the stream of water. The turbine is coupled to a generator for generating electrical energy. Each module may have submerged decomposition means for decomposing water into hydrogen and oxygen using the electrical energy generated. The modules are provided with means to control the depth of the modules below water level, and furthermore with means for automatically orienting the front of the modules—viewed in the longitudinal direction of the turbines—to the direction of flow of the water or an angular position deviating therefrom.
    Type: Grant
    Filed: November 13, 2000
    Date of Patent: April 1, 2008
    Inventor: Peter Alexander Josephus Pas
  • Patent number: 7351441
    Abstract: An easily dispersible granule of soybean protein having powdery soybean protein whose surface is coated with a carbohydrate, which is not readily digestible, wherein the carbohydrate is present in an amount of at least 5 parts by weight per 100 parts by weight of the powdery soybean protein. A method for preparing such an easily dispersible granule of soybean protein in which powdery soybean protein is granulated while the powder is sprayed with an aqueous solution containing a carbohydrate which is not readily digestible and which is characterized by using at least 5 parts by weight of the hardly digestible carbohydrate per 100 parts by weight of the powdery soybean protein is also shown. An alternative method involves spraying a dry mix of soybean protein and not readily digestible carbohydrate with lecithin in water, and removing the water from the resultant lecithin-coated mix.
    Type: Grant
    Filed: January 22, 2003
    Date of Patent: April 1, 2008
    Assignee: Archer-Daniels-Midland Company
    Inventors: Koji Tsukuda, Yasuhiro Hoshii, Thomas V. Gottemoller
  • Patent number: 7353149
    Abstract: Contact of rigid bodies is simulated with friction. A contact point is determined as a mid point between closest points on each body. An integrated relative velocity (IRV) vector is computed, and is minimized by applying forces to both bodies. If the IRV value exceeds a threshold the bodies are deemed to be sliding. Non-penetration constraint and friction values are determined in separate processes and the output of one is fed to the other.
    Type: Grant
    Filed: April 24, 2002
    Date of Patent: April 1, 2008
    Assignee: Telekinesys Research Limited
    Inventors: Oliver Strunk, Thomas Liss, Oliver Gross
  • Patent number: 7351787
    Abstract: A process for preparing activated polyethylene glycols is disclosed. In some embodiments, the process includes reacting a molten polyethylene glycol with an activator. In other embodiments, the process includes reacting a polyethylene glycol with an activator in the absence of a solvent. The process may be carried out in an inert gas atmosphere, at a temperature at least 10° C. above the melting point of polyethylene glycol, and/or with the activator provided in molar excess of the polyethylene glycol. The invention further provides activated polyethylene glycols produced by this process and their use in a variety of pharmaceutical, medical, cosmetic and chemical applications.
    Type: Grant
    Filed: March 3, 2005
    Date of Patent: April 1, 2008
    Assignee: Bioartificial Gel Technologies, Inc.
    Inventors: Marie-Pierre Faure, Kirill Shingel
  • Patent number: 7349504
    Abstract: A method and system for mitigating interference in a communication system, comprising at least one base station and at least one terminal, are disclosed. The base stations and terminals communicate through a channel existing between them, and the channels include at least a first signal channel and a second signal channel. The method includes determination of channel, noise and self-interference characteristic, computation of a rate limit of the channels, computation of the rate assignment of the channels, and assignment of the computed rate assignments to the channels. In another aspect of the present invention, the method includes determination of channel characteristics; computation of a power control margin, self-interference characteristics, power control command; and assignment of the computed power control command to each communicating terminal and base station.
    Type: Grant
    Filed: March 18, 2005
    Date of Patent: March 25, 2008
    Assignee: Navini Networks, Inc.
    Inventors: Hang Li, Guanghan Xu
  • Patent number: 7350177
    Abstract: A configurable logic and memory block (CLMB) and a configurable logic device are disclosed. The CLMB includes one or more static random access memory (SRAM) cells, a first output module for generating a first output by reading at least one SRAM cell when the CLMB functions as an SRAM, a second output module for generating a second output by reading at least one SRAM cell when the CLMB functions as a program logic device (PLD), wherein data on one or more bitlines coupled to the SRAM cells are controllably feeding into the first and second output modules. The configurable logic device can provide various Boolean logic functions using pass gates.
    Type: Grant
    Filed: July 13, 2005
    Date of Patent: March 25, 2008
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shine Chien Chung, Yung-Chin Hou, Kun Lung Chen, Yu-Chun Wu
  • Patent number: 7348832
    Abstract: A voltage generation system for generating operating voltages for memory devices, especially non-volatile memories, from a single external high voltage source. In one embodiment, the system comprises an input terminal for receiving an external voltage, a charge pump for producing a first high voltage based on the external voltage to be higher than the external voltage, a first regulating circuit for regulating the first high voltage to a lower predetermined voltage, a second regulating circuit for generating a second high voltage based on the external voltage to be lower than the external voltage.
    Type: Grant
    Filed: March 20, 2006
    Date of Patent: March 25, 2008
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsiang-Tai Lu, Cheng-Hsiung Kuo, Yue-Der Chih
  • Patent number: D565436
    Type: Grant
    Filed: February 8, 2007
    Date of Patent: April 1, 2008
    Assignee: Vyro Games Ltd.
    Inventors: Phil McDarby, Darran Hughes, Daragh McDonnell
  • Patent number: D565741
    Type: Grant
    Filed: February 8, 2007
    Date of Patent: April 1, 2008
    Assignee: Biokit, S.A.
    Inventors: Kathleen Vincent, Mark Talmer, Gerhardt P. Schroeder
  • Patent number: D566687
    Type: Grant
    Filed: January 26, 2007
    Date of Patent: April 15, 2008
    Assignee: Helio, LLC
    Inventors: Matias Duarte, Harout Mkhitarian, Chan Hans Liu, Mun Gwen Chong