Abstract: A design tool for choosing and modifying features of a dot matrix display. The design tool allows a user to design and save a character set and then to enter and view text to be displayed using the character set. The user is able to modify features of the display and to immediately see the result of any modifications made. The user may further see a representation of a hardware display having features and characteristics selected by the user, and may modify the features as desired. As the modifications are made, they are reflected in the representation of the hardware display. The design tool allows the user to store numerical representations of the selected features and characteristics of the design in order to provide the numerical representations to personnel implementing a hardware embodiment of the design.

Abstract: Improved techniques for transmission and display of video data are described. A point of sale terminal includes a processor, memory and software executed by the processor to create frames of data and to analyze the frames of data to create differential data defining differences between preceding and succeeding frames of data. The differential data can be applied to the preceding frames to construct the succeeding frames. At least one frame is transmitted to an external video interface using an external connection such as a universal serial bus port. Differential data is also transmitted to the external video interface. The differential data is applied to the frame which has been transmitted in order to create succeeding frames. The frames of video data are displayed using a display connected to the video interface.

Abstract: A method of reading a plurality of bar codes during a scanning motion across a bar code scanner which enhances scanner operation. The method includes the steps of obtaining data from a detector in the bar code scanner, determining position information associated with the data, distinguishing data associated with each bar code using the position information, and assembling the bar codes from the data.

Abstract: Efficient techniques for computation of texture coordinates using scaled conversion operations for a 3D graphics pipeline utilizing a scaled floating point to integer instruction and a scaled integer to floating point instruction to significantly reduce memory requirements. A parallel array VLIW digital signal processor is employed along with specialized scaled conversion instructions and communication operations between the processing elements, which are overlapped with computation to provide very high performance operation. Successive iterations of a loop of tightly packed VLIWs are used allowing the graphics pipeline hardware to be efficiently used.

Abstract: Techniques for an electronic shelf label (ESL) system which uses a digital modulation technique for a modulated backscatter uplink from an ESL to a communication base station (CBS) which utilizes pseudo-random sequences instead of a single continuous wave frequency. The CBS transmits a message to an ESL using a Manchester coded amplitude modulated carrier. After receiving the message, the ESL responds by reflectively modulating a continuous wave (CW) signal with a pseudo-random code sequence. Multiple pseudo-random code sequences may be chosen, with each code sequence corresponding to a particular response. The code sequence is modulated onto a kHz carrier which is used to reflectively modulate the CW signal received from the CBS. The CBS then receives the reflectively modulated signal and correlates the received signal to determine message transmitted.

Abstract: Techniques for monitoring of storage usage and trends in a document image processing and storage system are described. A storage and retrieval monitor resides on a storage server and monitors the status of volumes and units on which data is stored, completed storage requests and pending storage and retrieval requests. The storage and retrieval monitor analyzes completed and pending storage requests in order to project usage trends over time, and also analyzes the storage status in order to determine the used and available space and the space dedicated to various units and classes of data such as documents and families of documents. The storage and retrieval monitor generates alerts when the available storage space falls below a predetermined limit. The alerts and the usage and status information are presented to a user through a user interface allowing easy access to the storage and usage information and the ability to select desired information for display.

Abstract: A mechanism is provided for efficiently storing a key and optionally additional data in an environment. A memory apparatus embodiment includes a plurality of memory banks and a conversion module. The number of memory banks is determined by at least the number of coordinates within an n-dimension format, each bank is associated to one of the coordinates within the n-dimension format. Each memory bank has at least a number of memory locations equal to the largest valid value for its associated coordinate. The conversion module converts a key into an n-dimension format, the n-dimension format defines a coordinate system where each coordinate represents a memory location within the associated memory bank. The conversion module stores the key into one memory location based on a policy which is dependent on the coordinates defined by the n-dimension format.

Abstract: Techniques for displaying promotional information by providing an electronic sign (ES) which displays promotional information, display slogans, bundled pricing, bulk pricing, and other types of information. The ES can be used by retailers to increase sales, provide an alternate technique for advertising and reduce costs. According to one aspect, an EPL computer reads an EPL/ES data file to determine if an entry is associated with an EPL or an ES. The EPL computer then reads a promotional message from a promotional data file. An index in the EPL/ES data file may be used to determine the correct promotional message. The EPL computer transmits a message to the ES which includes a command for the ES to display the promotional message. The ES then displays the promotional message, providing valuable information to customers who are in the process of making purchasing decisions. In one aspect, an ES displays promotional information associated with an offer and is not associated with any particular single item.

Abstract: An electronic price label (ESL) system with a reduced power consumption ESL is described. In one aspect, an ESL system and method conserves battery power by removing power from certain ESL components which are utilized to receive messages during time periods in which the ESL is not scheduled to receive messages. The host computer system transmits a power save command to the ESL instructing the ESL to cease downlink monitoring and remove power from at least a portion of the receiver circuitry. The power save command includes a start time and a predetermined time period, both which are stored in ESL registers. Alternatively, the power save command may include a start time and an end time. When the start time occurs, the ESL circuitry removes the power from the receiver and ceases downlink monitoring for messages, thus reducing the power consumed by the ESL.

Abstract: A digital signal processor for computing various types of complex multiplication is described. The digital signal processor operates in conjunction with registers, a multiplier, an adder, and a multiplexer The Registers store first and second complex operands. The multiplier simultaneously performs multiplications to produce each combination of products between the real and imaginary terms of the first and second complex operands. The multiplexer selects which produced products are added to or subtracted from each other based on the type of complex multiplication being performed. The adder simultaneously performs additions and subtractions, if necessary, to produce both real and imaginary results depending on whether the type of complex multiplication being performed is a conjugated operation. The registers store the results of the complex multiplication.

Abstract: Techniques for using imaging information computed from examining a scanner signal are described. When one or more objects passes within a field of view of a scanner, scan patterns emerging from one or more scanner windows and reflected from the objects back into the scanner windows produce one or more scanner signals. The scanner signals are processed to obtain beam position and beam length information to improve the accuracy of bar code decoding and to compute imaging information for objects within the field of view of the scanner. The imaging information for the objects is compared with bar code information for the objects. The expected number, size and shapes of objects indicated by the bar code information is compared with the actual number, size and shapes of objects in order to determine if valid scans occurred or if missed, double or otherwise erroneous scans occurred.

Abstract: An eventpoint chaining apparatus for generalized event detection and action specification in a processing environment is described. In one aspect, the eventpoint chaining apparatus includes a first processor which has a programmable eventpoint module with an input trigger (InTrig) input. The first processing element detects an occurrence of a first processor event (p-event) and produces an OutTrigger (OT) signal. The eventpoint chaining apparatus also includes a second processor which has a programmable eventpoint module with an input trigger (InTrig) input which receives the OT signal from the first processing element. The second processing element detects an occurrence of a second p-event and produces, in response to the OT signal received from the first processing element and the detection of a second p-event, an eventpoint (EP) interrupt signal.

Abstract: Techniques are provided for performing modular arithmetic on a key composed of many bits. One circuit implementation includes a distributor, one or more lookup tables and a plurality of adders. The distributor segments the key into a plurality of partitions. Each partition is based on a polynomial expression corresponding to a fixed size key. Each of the bits contained within the partitions are routed on a partition basis to one or more lookup tables, the routed bits acting as indices into the one or more tables. The lookup tables store precomputed values based upon the polynomial expression. The outputted precomputed values from one or more lookup tables are outputted to the plurality of adders. The plurality of adders add the bits from a portion of the routed partitions and the outputted precomputed values from the one or more lookup tables to form the binary residue.

Abstract: A retractable leash device is comprised of a housing with a handle, and a leash wound around an internal reel. The reel is biased by a spring to automatically retract the leash. A momentary unidirectional lock in the housing is arranged to be normally disengaged from unidirectional teeth on the reel. When the momentary unidirectional lock is actuated, the reel is engaged by a ratchet to prevent rotation in the release direction but permit rotation in the retract direction. A toggle lock in the housing is movable between an unlocked position away from the reel, and a locked position between cogs on the reel. A geared rotation damper is engaged with a concentric gear on the reel to limit retraction speed. A clip attached to the housing may be clipped around the leash when the leash is wrapped around a fixed object.

Abstract: A systematic approach to architecture and design of the instruction fetch mechanisms and instruction set architectures in embedded processors is described. This systematic approach allows a relaxing of certain restrictions normally imposed by a fixed-size instruction set architecture (ISA) on design and development of an embedded system. The approach also guarantees highly efficient usage of the available instruction storage which is only bounded by the actual information contents of an application or its entropy. The result of this efficiency increase is a general reduction of the storage requirements, or a compression, of the instruction segment of the original application. An additional feature of this system is the full decoupling of the ISA from the core architecture. This decoupling allows usage of a variable length encoding for any size of the ISA without impacting the physical instruction memory organization or layout and branching mechanism as well as tuning of the execution core to the application.

Abstract: A self-diagnosing electronic price label. The label communicates with a central processor in order to receive price information for display and to report the status of the label to the central processor. The label periodically runs a self-test program to verify proper operation of its components. If a component fails the self-test, the failure is reported to a central processor, and the central processor reports the failure for investigation. During normal operation, the label issues a signal to the central processor indicating normal operation. In the event of a failure, the label ceases to send the signal indicating normal operation. When the signal is not received as expected, the central processor reports the failure to receive the signal for investigation. This allows the central processor to be alerted to failures which disable communication between the label and the central processor.

Abstract: Port priorities are defined on a 32-bit word, 16-bit half-word, and 8-bit byte basis to control the write enable signals to a compute register file (CRF). With a manifold array (ManArray) reconfigurable register file, it is possible to have double-word 64-bit and single word 32-bit data-type instructions mixed with other double-word, single-word, half-word, or byte data-type instructions within the same very long instruction word (VLIW). By resolving a write priority conflict on the byte, half-word, or word that is in conflict during the VLIW execution, it is possible to have partial operations complete that provide a useful function. For example, a load half-word to the half-word H0 portion of a 32-bit register R0 can have priority to complete its operation while a 64-bit shift of the register pair R0 and R1 will complete its operation on the non-conflicting half-word portions of the 64-bit register R0 and R1.

Abstract: A checkout device including an element for shifting a scan pattern to an effective location for scanning. In addition to the optical element, the checkout device includes a bar code reader. The bar code reader includes a housing having an aperture for emitting scanning light beams. The checkout device further includes a security system in the housing and adjacent the aperture for deactivating security labels on scanned items.

Abstract: An interface source system providing at least two paths to load an instruction decode register of a coprocessor is disclosed. The interface source system includes an instruction port register, an instruction memory, an instruction decode register, and an interrupt vector table (IVT) stored in the instruction memory. The IVT stores an external instruction vector containing either a predetermined value indicating that the instruction decode register is to be loaded with contents from the instruction port register or an address of an instruction in the instruction memory. A first one of the at least two paths is used to load the instruction from the instruction memory containing the IVT if the external instruction vector contained the address of the instruction in the instruction memory. A second one of the at least two paths is used to load the instruction from the instruction port register if the external instruction vector contained the predetermined value.

Abstract: Systems and techniques for reading a radio frequency identification transponder are described. A transmit coil produces a transmit field to power and interrogate the transponder. A reference coil and a receive coil furnish inputs to a differential amplifier, balanced so that the differential amplifier produces a predetermined signal. The receive coil senses changes produced by the transponder, while the reference coil is relatively isolated from such changes. The differential amplifier produces an amplified signal based on the difference between the inputs from the receive coil and the reference coil, so that the signal produced by the differential amplifier is based on the field effect changes produced by the transponder.