Abstract: A system, method, and apparatus for the constant time, branchless conversion of decimal integers of varying size in ASCII format to a decimal integer in binary decimal format in a vector processor utilizing simultaneous conversion of the string to a binary format, followed by simultaneous multiplications of the binary result by appropriate powers of ten and a fixed number of steps of vector addition, followed by a final step of a scalar multiplication of a sign value.

Abstract: A method and circuits for monitoring and detecting an error in the static pervasive signals applied to input/output pins of an integrated circuit during functional operation of the integrated circuit. The method and circuits provide a signal signature of each of one or more groups of the static pervasive signals and then monitoring the signal signature for any change of logic level.

Abstract: The present invention provides a method and apparatus for converting, through add-on hardware and code, any of a variety of types and vintages of general purpose personal, laptop, or notebook computers to be an efficient, secure, dedicated system which run independently of the host system's resident operating system.

Abstract: A system and method of operation for a lithographic system having multiple exposure stations sharing one or more post-expose bake station and a centralized control system that schedules work through the expose station to the post-expose bake station while taking into consideration the patterning time for work pieces to be scheduled as well as the amount of post-expose delay allowable for the exposed work pieces.

Abstract: The present invention comprises a system, software, and method for the treatment of mask data that produces defects in resultant images produced in the fabrication of a mask, following identification of the defects. The invention involves identifying each exposure shot with certain information which when combined with similar information related to the defects is used to control the exposure tool to toggle or modulate the shots related to the defects and thus, eliminate the defects.

Abstract: The present invention relates to a method, apparatus, and system for monitoring photomasks used in the production of semiconductor wafers for defects, degradation or a combination thereof. The invention provides an integrated test structure on the photomask itself and a method of positioning the test structure in conjunction with the photomask for a masking layer of an integrated circuit. The integrated test structures provide for an in-situ electrical or electromagnetic monitor on the photomask that doesn't adversely affect the integrated semiconductor devices on the wafers during the lithographic masking process.

Abstract: The present invention describes a structure and method for reducing or eliminating the flatness distortion effects of a photomask assembly which occurs when a pellicle is mounted to the photomask. The invention is to perform a partial disconnection of the mounting area of the pellicle frame from the print area of the mask. An exemplary embodiment of the present invention achieves the distortion reduction or elimination using a trench in the photomask as the partial disconnection.

Abstract: A structure and method for fabricating a top strap in a magnetic random access memory, MRAM, comprising a damascene process forming a trench in a dielectric layer and resulting in a metal conductor clad on three sides by an inverted U-shape trench liner and cap made up of three layers consisting of a stack of a ferromagnetic material sandwiched between two layers of a refractory metal or an alloy of a refractory metal. First the two sidewalls of the trench are formed with the cladding layer, followed by filling the trench with the metal conductor. In preparing the structure for the capping layer, the metal conductor is recessed with an etch that is selective to the metal conductor over the sidewall stack. This preparation may be performed on selected metal filled trenches and blocked on others, such that after a final polishing step, only those metal conductors that received the recess operation will have the capping layer.