Abstract: A method of operating an intruder detector system comprising deploying plural intruder sensors in or adjacent a region to be protected, transmitting signals from each sensor to a processor, the signals relating to at least one local environmental ambient condition, processing the signals to determine a common ambient condition associated with the intruder sensors, transmitting a control signal to each of the sensors, and automatically adjusting the sensors in response to the control signal to substantially vary detection parameters thereof.

Abstract: A method of diagnosing a malfunction of a process control system which includes at least one closed loop control loop comprising measuring a histogram of tracking error of the control loop, determining distortion of the tracking error relative to a Gaussian distribution, and indicating a malfunction in the process in the event a deviation from the Gaussian distribution of the tracking error exceeds predetermined limits.

Abstract: A method of reconstructing a stream of digital frequency domain audio signal samples into audio signals comprising parsing the stream of samples and reconstructing subband data in the frequency domain, processing the subband data to obtain a processed frequency domain digital audio signal, and constructing a time domain audio output signal from the processed frequency domain digital audio signal.

Abstract: A jitter test system for a clock and data recovery unit (CRU) is comprised of a data generating apparatus, apparatus for clocking the data generating apparatus with a jittered clock, apparatus for applying a stream of data generated by the data generating apparatus that has been jittered by the jittered clock to an input of the CRU, and apparatus for detecting a bit error rate of a data signal output from the CRU.

Abstract: A sensor cable formed of a center conductor surrounded by dielectric material and first and second layers. The first layer is formed of a gapped conductive material surrounding the dielectric material. The second layer has predetermined conductivity and at least covers the gaps in the conductive material of the first layer. The predetermined conductivity and thickness of the second layer is such that the skin depth in the second layer at an operating frequency of the cable is much greater than the thickness of the second layer, and inductive coupling into or out of the cable through gaps in the second layer is at least an order of magnitude greater than capacitive coupling into or out of the cable through gaps in the second layer.

Abstract: A method of testing a digital memory comprised of bit storage locations, comprising writing a bit to a first bit storage location, then driving the stored bit sequentially through a plurality of the bit storage locations, reading a last bit storage location of the plurality of bit storage locations, and testing a bit read from the last bit storage location.

Abstract: A charge pump comprising a first branch PMOS FET having a source connected to a voltage source and a drain connected to an output node, a second branch NMOS FET having a drain connected to the output node and a source connected to a ground node, first apparatus for selectively switching a gate of the PMOS FET between its source and a first bias voltage source, and second apparatus for selectively switching a gate of the NMOS FET between its source and a second bias voltage source, the bias voltages being of magnitudes such that the first branch PMOS FET and second branch NMOS FET will source and sink the same magnitude of current when the FETs are fully conducting.

Abstract: A programmable frequency synthesizer comprised of a phase locked loop (PLL) including a current controlled oscillator (ICO), a level translator for receiving output signals from the ICO wherein the output signals have a finite slew rate, a reference source of signals, a phase-frequency detector for receiving signals from the reference source and output signals generated by the level translator and for providing pulse signals to the ICO having pulse widths which are directly proportional to phase difference between the signals from the reference source and the output signals from the level translator, and apparatus for varying the slew rate of the output signals from the ICO wherein the duty cycle and thus the frequency of output signals of the level translator may be varied.

Abstract: A method of controlling the display of graphics data on a computer display, the computer comprising a draw engine, comprised of detecting predetermined logical condition of a draw operation for display, saving the state of the draw engine, performing a new draw operation, and restoring the state of the draw engine.

Abstract: A pulse receiver, comprising a pair of complementary symmetry metal oxide silicon (CMOS) common gate amplifiers connected between a 5 volt supply (ECL) voltage rail and an ECL ground (AGND), for receiving a pair of pulse input signals IN and INB and for providing a pair of first pulse signals, CMOS apparatus for distorting the first pulse signals, to create second pulse signals from the converter having a duty cycle having a longer low logic level interval than high logic level interval, a CMOS latch for receiving and latching the second output signals from the common gate amplifiers at logic levels compatible with circuits formed of CMOS elements, a CMOS double to single ended converter connected between a VDD voltage rail and VSS ground, for receiving the latched output signals, apparatus for providing an output signal referenced to VDD and ground from the converter.

Abstract: A method of drawing moving images on a graphics display comprising (a) receiving data defining an input image in a predetermined resolution, (b) commanding a graphics processor to draw a corresponding image frame on a display having a number of scanning lines which is a multiple m of a number of scanning lines of the input image and a multiple n of a number of pixels in a horizontal line of the input image, (c) drawing successive lines of the input image on a first and on each m.sup.th scanning line of the graphics display, while stretching each pixel on each drawn line over n pixels, (d) copying each drawn line on respective immediately following m-1 lines, and (e) repeating steps (b)-(d) for successive frames of the input image.

Abstract: A dynamic random access memory (DRAM) having pairs of bitlines, each pair being connected to a first bit line sense amplifier, wordlines crossing the bitline pairs forming an array, charge storage cells connected to the bitlines, each having an enable input connected to a wordline, the bit line sense amplifiers being connected in a two dimensional array, pairs of primary databuses being connected through first access transistors to plural corresponding bit line sense amplifiers in each row of the array, apparatus for enabling columns of the first access transistors, databus sense amplifiers each connected to a corresponding data bus pair, a secondary databus, the secondary databus being connected through second access transistors to the databus sense amplifiers, and apparatus for enabling the second access transistors, whereby each the primary databus pair may be shared by plural sense amplifiers in a corresponding row of the array and the secondary databus may be shared by plural primary databus pairs.

Abstract: A method of linking peripheral devices to a single interrupt procedure in a computer is comprised of storing in an interrupt vector table of a BIOS ROM, a first pointer to an interrupt service routine related to one of a group of peripheral devices which use the same interrupt request (IRQ) on the same software interrupt vector, and storing further pointer in each one of the peripheral devices to another unique one of the peripheral devices in the group.

Abstract: An electrostatic discharge (ESD) protection structure for protection of a circuit to which an operation voltage is to be applied, comprising a silicon controlled rectifier (SCR) connected between ground and a pad of the circuit to be protected, the SCR including a resistor apparatus connected to the pad for controlling the breakdown voltage of the SCR, and apparatus for controlling the resistor apparatus to a high resistance value in the absence of the application of the operation voltage whereby the SCR is controlled to break down at a low ESD voltage which is lower than a circuit damaging voltage, and to be of low resistance value upon the application of the operation voltage whereby the SCR is controlled to break down at an ESD voltage which is higher than the low ESD voltage.