Abstract: A semiconductor nonvolatile memory cell comprised of a p-type silicon well 12, an n+ drain 8 and an n+ source 10, the source and the drain regions defining an channel region 7. On top of the well 12 there are laminated a thin silicon dioxide film 2 served as a gate oxide, a polysilicon layer 32 and a SrTiO3 layer 34 comprised of a high dielectric substance, in respective order. Further on top of these layers, there is formed a polysilicon layer 36 served as gate electrode. By using the memory cell and appropriate select transistors, a semiconductor nonvolatile memory device is constructed.
Abstract: A bidirectional digital data communication system which generate phase coherent upstream clock and carrier signals from recovered downstream clock generated from a master clock in a central unit. The preferred species uses any downstream clock rate and generates a phase coherent upstream clock so long as the two clock rates can be related by the ratio M/N where M and N are integers. One embodiment uses an MCNS downstream and an SCDMA upstream and uses MNCN timestamp messages in the downstream to achieve an estimate of RU frame offset prior to establishing frame alignment using a ranging process. The use of timestamp messages to estimate the offset is aided by a low jitter method for inserting timestamp messages by avoiding straddling of MPEG packet headers with the sync message. Clock slip is detected by counting upstream clock cycles over a predetermined downstream clock interval and the RU transmitter is shut down if slip is detected to prevent ISI interference from misaligned codes.
Type:
Grant
Filed:
March 1, 2001
Date of Patent:
March 5, 2002
Assignee:
Terayon Communications Systems, Inc.
Inventors:
Michael Grimwood, Jim Knittel, Paul Richardson, Selim Shlomo Rakib, Paul Alan Lind, Doug Artman
Abstract: This relates to a digital data recovery system for decoding group coded data bits stored on magnetic tape whereon a "1" is represented by a flux reversal and an "0" is represented by the absence of a flux reversal with no more than two successive zeros throughout the data record. Input logic detects transitions of input data and forwards this information to an envelope detector which determines if subsequent transitions represent valid data. The presence of valid data enables a data rate detector which determines the average data rate. An output sequencer determines when a decoded output data bit should be generated and its proper polarity.