Abstract: In a data processing system, including a memory subsystem and a CPU subsystem coupled to the memory subsystem for processing program instructions stored in the latter, the present disclosure describes an arrangement for improving the handling of type 1 dyadic instructions in the CPU subsystem. Type 1 dyadic instructions generally involve the logical processing of two operands in the CPU, and the writing of an associated result function to a designated location in memory at which one of the two operands originated. In accordance with the present invention, the result is compared with the origin operand at an appropriate instant in the instruction execution sequence and the writing operation is conditioned on this comparison. If the compared values are different the writing operation is allowed to continue, but if the compared values are equal the writing operation is skipped; thereby eliminating CPU and memory operating cycles otherwise required for completing the writing action.

Abstract: In a ring-structured data communication network, in which plural data processing systems exchange data and control information on a full duplex peer to peer basis, systems are presently architected to assign at least three I/O subchannels (i.e. at least three device addresses) to respective ring interface adapters. At least two of these subchannels are dedicated for providing separate input paths from the ring to at least two associated program-assignable areas in their system's main store, and a third of these subchannels is dedicated as an output path from the system's store to the ring. Collectively, these subchannels can sustain two input transfer processes and one output transfer process concurrently. One of these input processes is associatable with a locked mode of adapter operations which provides a non-blockable path for data transfer from a selected (remote) station on the ring to the respective system's main store.

Abstract: Multiprocessing systems having changeable CPU configurations generate unique changeable identifications (ID's). These are presented by I/O channels over various I/O connection paths, in association with special path defining commands and function data. Related path state indications are stored peripherally in path map tables and define path group associations for sustaining path-independent I/O operations. When a device is reserved via one path in a path group the reserve affiliation is extended automatically (in the path tables ) to each path in the group, thereby rendering each path accessible in a reserved mode. The path defining commands are used for adding paths to, resigning paths from and disbanding groups. Special sensing commands are used for sensing path reservation and grouping states. When a command for adding or resigning a path is presented to a reserved device via one path in a group the reserve is automatically realigned to the enlarged or reduced group.

Abstract: Operations to prepare a secondary paging store for a data transfer relative to a central processor main store are overlapped in time with chaining operations of an input-output channel relative to the main store for preparing a command defining the transfer operation. In a preferred embodiment the paging store is organized for sequential access to page records and the operations to prepare the paging store include a calculation of a "roll mode" displacement factor which defines a randomly chosen displacement position in a designated page area for beginning the transfer with minimized latency. This factor is calculated as a function of channel operational characteristics as well as the bit timing rate of the paging store. The displacement calculation is also adapted for a paging store having different timing rates for transferring data and regenerating stored data.

Abstract: Secondary storage subsystems exchange messages and data with host data processing systems and also forward messages between host systems. Host systems thereby communicate with each other in addition to having access to data in subsystem storage. Access to subsystem storage is initiated by a "request" sent from a host to the subsystem. Each request is a message containing an array of one or more commands, each command specifying a transfer of data or a control function to be performed by the subsystem. A subsystem may process more than one request at a time. It also may process the commands in a request in an arbitrary sequence suited to the availability of subsystem resources and data links to host systems. After all commands in a request have been processed the subsystem transmits an associated "completion" message to the host system which originated the request. The completion message indicates the status of completion or abnormal termination of each command in the associated request.

Abstract: Interrupt requests of different priorities, presented by various interrupt sources (0 to 3), are transferred through control ST, in an associative storage and selection process, into preprocessing elements PE0 and PE1. These elements are variably assigned by controls ST to receive and preprocess requests of associated priority. The preprocessing generates a starting address of a program routine for servicing the respective request. This address is transferred to a common processor which executes the routine. The preprocessing elements can be structured to rapidly generate a succession of different starting addresses relative to several interrupt requests having the priority assigned to that element.

Abstract: A new instruction called Test Subchannel assures that one processor will not begin an I/O operation with device status information that has been outdated by an operation of another processor. When a device has status to present, a status pending bit and an interruption pending bit are set in the channel subsystem and an interruption request is made. When a processor accepts an interruption, the channel system resets the interruption pending bit but not the status pending bit. The processor that accepts the interruption updates the unit control block (UCB) in main store and resets the status pending bit in the subchannel unless the UCB has been locked by another processor that is starting an I/O operation on the same device. This invention prevents the other processor from operating with outdated status information in the UCB. A processor that has locked the UCB uses Test Subchannel to test the Status Pending bit in the subchannel. If status is pending, the processor executes a routine to update the UCB.

Abstract: A central processor through an asynchronous service processor, selectively resets an input/output channel designated in an instruction called Clear Channel that is executed by the central processor. As part of the execution of this instruction, the service processor also communicates a reset signal to the peripheral equipment associated with that channel in case the designated channel is malfunctioning and cannot relay a reset signal normally to the peripheral equipment associated with the designated channel. The reset signal for the peripheral equipment is supplied through a connection between the service processor and particular lines in I/O interface cables of that channel. Programming routines that use the Clear Channel instruction are designed to preserve the integrity of data held by peripheral equipment that is associted with two channels when the peripheral equipment has exclusive affiliations with the designated channel.

Abstract: Latency of a cyclic bulk storage device attached to a CPU and a main storage through standard channel facilities is reduced without modification of the channel and CPU hardwares. The storage device is divided into a plurality of randomly accessible pages each having parallel cyclic tracks. Each page is subdivided into two sequentially and cyclically accessible Sectors 0 and Sector 1. Parallel bits on different tracks form bytes. Data are transferred byte by byte between a selected page of the device and a specified one-page data area in the main storage. A channel program is constructed using three commands (CCWs); a Seek Page command followed by two different Read or Write commands. At the end of the Seek Page operation, a control unit determines which of Sector 0 or 1 is more immediately accessible.

Abstract: In a time division multiple access (TDMA) system, for "multi-path" data communication via satellite repeater, the form of transmitted data is varied adaptively to maintain error-free transmission under varying noise conditions. Adjustments are made on a path selective and channel selective basis to protect only the most vulnerable data in specific transmission paths experiencing noise deterioration. Accordingly any multi-channel burst may contain channels of data in both protected and unprotected forms. A predetermined portion of each channel containing data in unprotected format is used explicitly to designate the destination of the accompanying data and implicitly to distinguish the data format as unprotected. In protected format data including error protective coding is transmitted in two contiguous channels along with information in the first channel explicitly distinguishing the protected format.