Patents Represented by Attorney R. M. Wallace
  • Patent number: 4394769
    Abstract: The ring counter of this invention is self-initializing and is operable at a clock frequency corresponding to four gate delays and comprises a plurality of master of slave flip-flops, in which this high speed capability is attained by using non-inverting feedback between the first and last flip-flops and by operating the master and slave of each in complementary fashion without requiring the use of a complementary clock signal. The non-inverting feedback takes advantage of the inherent delay between the response of the complementary outputs of each flip-flop.
    Type: Grant
    Filed: June 15, 1981
    Date of Patent: July 19, 1983
    Assignee: Hughes Aircraft Company
    Inventor: John M. Lull
  • Patent number: 4360745
    Abstract: The capacitance of a compensating reverse biased diode is added to the capacitance of a pn junction formed by surface depletion and inversion in a charge coupled device having variations in depletion capacitance which are to be compensated. Because the compensating diode is connected in an opposite sense with respect to the pn junction, an increase in small signal variations in the potential across the pn junction causes a decrease in small signal variations in the potential across the compensating diode. The resulting change in the capacitance of the pn junction is accompanied by a corresponding opposite change in the capacitance of the compensating diode so that the combined capacitance of the two elements remains nearly constant during all small signal variations in potential.
    Type: Grant
    Filed: May 26, 1981
    Date of Patent: November 23, 1982
    Assignee: Hughes Aircraft Company
    Inventor: Paul R. Prince
  • Patent number: 4331889
    Abstract: In a charge transfer device imager, photodetector output current is accumulated and stored during an integration period in an analog potential well in the substrate surface potential adjacent the photodetector, the analog well being reset each time the detector changes the amount of stored charge by a preselected fraction of the storing well capacity, simultaneously incrementing a digital count. At the end of each integration period, both the contents of the analog well and the digital count are read into an output register. As a result, the length of the integration period may be significantly extended without regard to the charge storing capacity of the charge transfer device, thus improving the signal-to-noise ratio and the dynamic range of the imager. In the preferred embodiment, the amount of charge stored in the analog potential well is sensed by sensing the potential of the photodetector, where the photodetector comprises a diode diffusion in the substrate.
    Type: Grant
    Filed: June 3, 1980
    Date of Patent: May 25, 1982
    Assignee: Hughes Aircraft Co.
    Inventor: William J. Parrish
  • Patent number: 4331874
    Abstract: As CCD circuit for restoring to a common DC level, data received from a plurality of detector channels of a scanned array so as to overcome the effect of variations in detector parameters and other non-uniformities in the circuit. The DC correction value is established during retrace time by storing a representative time integrated data charge packet when energy from a cold reference surface is being applied to the detectors. During the scan time of the field of view by the detectors the representative charge packet is utilized to provide a DC restoration or correction charge to each data charge packet received from the detectors. The system thus standardizes to a common DC level, the output data from a plurality of channels.
    Type: Grant
    Filed: July 2, 1980
    Date of Patent: May 25, 1982
    Assignee: Hughes Aircraft Co.
    Inventors: James S. Duncan, Michael Y. Pines
  • Patent number: 4327477
    Abstract: Defects in the metal step coverage of a thin film semiconductor device are removed by annealing the metal layer with a pulsed electron beam.
    Type: Grant
    Filed: July 17, 1980
    Date of Patent: May 4, 1982
    Assignee: Hughes Aircraft Co.
    Inventors: Giora Yaron, Eliyahou Harari, LaVerne D. Hess, Yueh Y. Ma
  • Patent number: 4173767
    Abstract: The invention concerns CMOS integrated circuits including an arrangement to prevent regenerative bipolar current flow between complementary transistors in the circuit.In one particular form, the invention provides a CMOS inverter comprising an N-type substrate in which is formed a P-channel MOS transistor together with a P-type well having therein an N channel MOS transistor, the drain of the P-channel transistor being connected to the drain of the N-channel transistor, and there being disposed in the N-type substrate between the said transistors, a P-type region preferably extending to the depth of said P-type well and electrically connected to the source of the N-channel transistor. The effect of the P-type region aforesaid is to preclude the likelihood of regenerative bipolar conduction becoming established, in use of the inverter, in the substrate, which bipolar conduction might otherwise cause destruction of the CMOS circuit.
    Type: Grant
    Filed: May 5, 1978
    Date of Patent: November 6, 1979
    Assignee: Hughes Aircraft Company
    Inventor: Alastair K. Stevenson