Abstract: A method for determining a change in the SAF-TE enclosure status and a change in the SAF-TE device slot status, each with a single issuance of one new command, replacing countless re-issuance of similar commands. Use is made of a common disconnection/reconnection capability as well as a tagged command queuing technique, such that multiple types of status changes in a SAF-TE enclosure are concurrently determined. Since each of the new commands described here is initiated by the host adapter, the host adapter is prepared for receiving asynchronously a changed status from the reconnecting target device such as a SEP whenever it becomes available, without resorting to use of a complex SCSI protocol known as “asynchronous event notification.

Abstract: A method, computer readable medium, apparatus and RAID controller for performing nondestructive write testing is disclosed. For data storage devices divided into sectors, the present invention performs nondestructive write testing by writing data to the sectors, reading data written to the sectors, and comparing the data written to the data read to detect errors. To increase efficiency, sectors previously written by a host or other computer are tracked, allowing sectors not previously written to be tested without saving and restoring data in the sectors. To locate the sectors written to by the host computer, write indicators such as a sector written indicator, a sector stripe written indicator, and a stripe written indicator are maintained. Upon detecting a defective sector, a new sector is allocated, and the defective sector is replaced by the allocated sector.

Abstract: Network architecture, computer system and/or server, circuit, device, apparatus, method, and computer program and control mechanism for managing power consumption and workload in computer system and data and information servers. Further provides power and energy consumption and workload management and control systems and architectures for high-density and modular multi-server computer systems that maintain performance while conserving energy and method for power management and workload management. Dynamic server power management and optional dynamic workload management for multi-server environments is provided by aspects of the invention. Modular network devices and integrated server system, including modular servers, management units, switches and switching fabrics, modular power supplies and modular fans and a special backplane architecture are provided as well as dynamically reconfigurable multi-purpose modules and servers.

Abstract: A system and method for performing tangent space lighting in a deferred shading graphics processor (DSGP) encompasses blocks of the DSGP that preprocess data and a Phong shader that executes only after all fragments have been preprocessed. A preprocessor block receives texture maps specified in a variety of formats and converts those texture maps to a common format for use by the Phong shader. The preprocessor blocks provide the Phong shader with interpolated surface basis vectors (vs, vt, n), a vector Tb that represents in tangen/object space the texture/bump data from the texture maps, light data, material data, eye coordinates and other information used by the Phong shader to perform the lighting and bump mapping computations. The data from the preprocessor is provided for each fragment for which lighting effects need to be computed. The Phong shader computes the color of a fragment using the information provided by the preprocessor.

Abstract: Adaptive write policy for handling host write commands to write-back system drives in a dual active controller environment. Method for adaptive write policy in data storage system, where data storage system includes host system connected to primary controller and alternate controller. Controllers are coupled to system drive that includes one or more disk storage devices. Primary is connected to first memory and alternate is connected to second memory. Primary and alternate manage data storage system in dual-active configuration. Primary controller receives host write command from host system and write data request includes host write data. When system drive is configured with write-back policy, primary determines whether host write command encompasses an entire RAID stripe, and if so, primary processes host write command in accordance with write-through policy. Otherwise, primary processes command in accordance with write-back policy.

Abstract: A media server system and method are disclosed for playback of digital media. For playback, header information associated with a complex asset is received. The header information comprises information for initializing a decoder (56) for playback of the complex asset. Artificial headers (54) for the complex asset are then created using the header information. A digital packet stream for the complex asset is received and passed decoder (56) for playback. During playback, artificial headers (54) are injected as appropriate for initializing the decoder (56) for playback of the complex asset. In one implementation, the complex asset can be a clip asset (100), a parallel asset (102), a sequential asset (106) or a composite asset (110).

Abstract: A method and apparatus are provided for dynamically creating an executable image from an Object File Format (OFF) file stored in a reserved area 175 of one of a plurality of data storage devices 125 in a memory system 100. In the method, a controller 105 having a Programable Read Only Memory (PROM) 160, Random Access Memory (RAM) 155 and a Central Processing Unit (CPU) 150 is coupled to the plurality of data storage devices 125. The memory system 100 is initialized using an initial boot sequence stored in the PROM 160. This initialization can include a hardware discovery sequence to identify all hardware present in the memory system 100. Data relating to the discovered hardware is read from the OFF file and translated from an object format into an executable image that is assembled in RAM 155. Optionally, the PROM 160 is an Electronically Erasable PROM (EEPROM) and the assembled executable image is stored in the EEPROM replacing the initial boot sequence.

Abstract: Apparatus and methods for rebuilding logical I/O devices in a cluster computer system. The apparatus include controllers programmed to cooperate towards this end. The apparatus has first and second nodes with respective bus controllers communicatively coupled to each other and to the logical I/O device by means of a bus. The first controller receives a request to rebuild the logical I/O device and, in response, conditionally communicates a rebuild request for the logical I/O device over the bus to the second controller. (The logical I/O device can be a logical device depending from a multi-logical-device, third controller.) Before conditionally communicating, the apparatus determines whether a rebuild of a logical I/O device is already in progress and, when a rebuild is already in progress, aborts the new request to rebuild. When an rebuild is not already in progress, the apparatus then sets a state variable to indicate that a rebuild is now in progress.

Abstract: The present invention provides a method and apparatus for performing an inverse modified discrete cosine transform (IMDCT) on at least one block of spectral coefficients representing an information signal in the frequency domain. The IMDCT provides an IMDCT output including at least one block of processed samples in the time domain. The new and novel method of the present invention includes converting spectral coefficients in the block of spectral coefficients to provide a block of frequency domain processed complex samples and processing the block of frequency domain processed complex samples into the block of processed samples in the time domain.

Abstract: A deferred shading graphics pipeline processor and method are provided encompassing numerous substructures. Embodiments of the processor and method may include one or more of deferred shading, a tiled frame buffer, and multiple-stage hidden surface removal processing. In the deferred shading graphics pipeline, hidden surface removal is completed before pixel coloring is done. The pipeline processor comprises a command fetch and decode unit, a geometry unit, a mode extraction unit, a sort unit, a setup unit, a cull unit, a mode injection unit, a fragment unit, a texture unit, a Phong lighting unit, a pixel unit, and a backend unit.

Abstract: A deferred graphics pipeline processor comprised of a mode extraction unit and a Polygon Memory associated with the polygon unit. The mode extraction unit receives a data stream from a geometry unit and separates the data stream into vertices data, and non-vertices data which is sent to the Polygon Memory for storage. A a mode injection unit receives inputs from the Polygon Memory and communicates the mode information to one or more other processing units. The mode injection unit maintains status information identifying the information that is already cached and not sending information that is already cached, thereby reducing communication bandwidth.

Abstract: Structure, method, and computer program for an explicitly tunable device controller. Method supports high-performance I/O without imposing additional overhead during normal input/output operations. Tuning is performed during explicit pre-I/O operation phase. In one embodiment, invention provides a method for tuning device controller operating characteristics to suit attributes of a data stream in which the method comprises: monitoring a data stream and collecting attributes of the monitored data stream; generating performance metrics of the data stream based on the collected attributes and a plurality of different assumed device controller configurations; comparing expected performance of the plurality of different device controller configurations for effectiveness with a future data stream having similar data stream type attributes to the monitored data stream; and selecting device controller characteristics to provide an effective match between the data stream type and the device controller configuration.

Abstract: Structure and method for efficient failover and failback techniques in a data storage system utilizing a dual-active controller configuration for minimizing a delay in responding to I/O requests from a host system following a controller failure is described. A stripe lock data structure is defined to maintain reservation status or stripe locks of cache lines within data extents that are part of a logical unit or storage volume. When a controller fails, dirty cache line data of a failed controller is taken over by a survivor controller. The stripe lock data structure is used to process I/O requests from a host system, by the failed controller. The data storage system functions in a single-active configuration until the dirty cache line data is flushed to one or more storage volumes, by the survivor controller. The inventive structure and method provide utilize a storage volume reservation system. The stripe lock data structure is defined in memory within each of the two or more caching controllers.

Abstract: A mechanism that allows an application program running on a processor, to send data to a device using a medium that temporarily stores data and changes the order of the data dispatch on the way to the device. An inventive Random-In-First-Out (RIFO) buffer or memory device that restores the original order is provided. Several alternative approaches for implementing the RIFO control mechanisms for write efficiency and correctness. Method for use in conjunction with a data processing system having a host processor executing write instructions and communicating results in the form of symbols generated by the write instructions to at least one hardware device coupled to the host processor for receiving the symbols from the host processor, where the method preserves a predetermined order in which the symbols are received by the hardware device.

Abstract: Structure, apparatus, and method for performing conservative hidden surface removal in a graphics processor. Culling is divided into two steps, a magnitude comparison content addressable memory cull operation (MCCAM Cull), and a subpixel cull operation. The MCCAM Cull discards primitives that are hidden completely by previously processed geometry. The Subpixel Cull takes the remaining primitives (which are partly or entirely visible), and determines the visible fragments.

Abstract: Combined Digital-Analog Signal Processors, Waveforms with Time Constrained Signal (TCS) response and Long Response (LR) filtered Bit Rate Agile (BRA) Modulation-Demodulation (Modem) Format Selectable (MFS) and Code Selectable (CS) system implementations for Interoperable Multiple Standard Enhanced GSM, CSMA, TDMA, OFDM, and third-generation CDMA, W-CDMA and B-CDMA systems and associated methods. Systems include Feher's Gaussian Minimum Shift Keying (GMSK or FGMSK) and Feher's Quadrature Phase Shift Keying (FQPSK) systems combined with Adaptive Antenna Arrays (AAA), Pseudo-Error (PE) based Non-Redundant Error Detection (NRED) controlled IF adaptive equalizers, smart antenna and smart diversity systems which have spectral/RF power efficiency and enhanced end-to-end performance.

Abstract: An indexing method for allowing a viewer to control the mode of delivery of program material. By mapping from time to data position, data delivery can begin at any selected time in the program material. The indexing method also provides for controlling data delivery to begin at the beginning of a frame of data. A synchronizing method is provided to minimize a time offset between audio and video data, particularly in environments using groups of pictures.

Abstract: Radio system including mixer device and switching circuit and method having switching signal feedback control for enhanced dynamic range and performance. Radio apparatus including: local oscillator input port for receiving periodic sinusoidal local oscillator signal; drive circuit for generating a substantially square-wave two-voltage level switching signal including: phase splitter circuit, voltage potential isolation circuit, and square wave signal generation circuit; FET mixing device; input/output signal separation circuit; analog-to-digital converter; and feedback control circuit. Radio tuner apparatus including low-band signal processing circuit; high-band signal processing circuit including first mixer circuit operating as an up-frequency converter, amplifier circuit, second mixer circuit operating as a down-frequency converter, and feedback control circuit for adjusting a duty cycle of a mixer switching device; signal combining circuit and output processing circuit.

Abstract: An apparatus (100) and method are provided for polishing a substrate (105) that achieves a high-planarization uniformity. In one embodiment, the apparatus (100) includes a subcarrier (165) with a lower surface (170), a flexible member (245) extending across the lower surface, and a control-insert (280) disposed between the flexible member and the lower surface. The flexible member (245) has a surface adapted to press the substrate against a polishing pad. The control-insert (280) inhibits non-planar polishing by providing a variable removal rate across the substrate surface. The control-insert (245) can be an annular ring (280A) located near an outer edge of the flexible member (245) to control the removal rate near an edge of the substrate (105), or a disk (280B) near a center (290) of the flexible member to control the removal rate near a center of the substrate. The removal rate can be further controlled by varying a cross-sectional thickness of the control-insert (245).

Abstract: A circuit and special cable which allow a single DB9 connector to provide a standard RS-232 interface to a RAID controller in single RAID controller systems or to provide a controller-to-controller communication link for messaging, control and status signals when the special cable is used to interconnect two RAID controllers in a dual-active system.