Abstract: An array fed reflector antenna includes a reflector and a distributed feed array. The reflector has a portion with a dual parabolic shape. The distributed feed array transmits and receives a plurality of electromagnetic energy beams simultaneously, and is positioned adjacent the reflector so that the reflector reflects the transmitted and received electromagnetic energy beams. The distributed feed array is offset from the reflector so that a plane wave formed by the transmitted electromagnetic energy beams reflected by the reflector will not substantially impinge the distributed feed array. The antenna also has a beam switching network which is a hybrid network for selectively actuating separate but overlapping portions of the distributed feed array to produce two transmit elevation beams.

Abstract: An electric power system having power supplies connected in parallel to a common bus includes a voltage feedback and current feedback loop for each supply. A voltage feedback signal and a current feedback signal are combined with a reference signal to produce an error signal. The output voltage of each supply is controlled in response to its corresponding error signal, to achieve current sharing and redundancy without interconnections among the control circuits of the various supplies.

Abstract: A two-loop superconducting sigma-delta analog-to-digital converter includes a first superconducting inductor to which the analog signal is applied. A resistor converts to current in the first inductor to a voltage which is applied to a second superconducting inductor. The current in the second inductor, which increases quadradically with time, is applied to an overdamped Josephson junction which kicks back a single quantum voltage pulse each time its critical current is exceeded. This pulse reduces the current in the second inductor and serves as a digital ONE output. The pulses are also applied to an underdamped Josephson junction in a feedback pulse generator which latches at its gap voltage for the remainder of a half cycle of an ac bias current.

Abstract: A method for determining the spacial relationship between concealed elongated conductors wherein a test signal is coupled to a first concealed conductor and conductively coupled to a second adjacent concealed conductor. The relative direction of the current of the test signal on the second conductor is measured on opposite sides of the first conductor. An indication of the relative directions of the current of the test signal on opposite sides of the first conductor can be used to determine if the two conductors are separated or in contact with each other. If the relative direction of the test signal radiated from the second conductor is the same on opposite sides of the first conductor, then the two conductors are separated from each other. If the relative direction of the test signal radiated from the second conductor is opposite on opposite sides of the first conductor, then the two conductors are in contact with each other.

Abstract: Superconducting digital logic circuits constructed in accordance with this invention include a circuit branch having first and second Josephson junctions electrically connected in series with each other, with a junction point between the first and second Josephson junctions connected to a neutral point; a positive bias voltage is connected to one end of the circuit branch, and a negative bias voltage is connected to a second end of the circuit branch; a first rail for applying a first input voltage signal, having a first polarity, and for extracting a first output signal is connected to one end of the circuit branch; and a second rail for applying a second input voltage signal, having a second polarity, and for extracting a second output signal is connected to the other end of the circuit branch. This invention encompasses both the above circuit and the method of signal processing performed by such circuits.

Abstract: Superconducting timed gate array cells for use in single-rail logic circuits are provided by adding inputs to modified variable threshold logic (MVTL) timed inverter circuits. Data signals which are inphase with a first phase of a power source are coupled to gate array cells in which Josephson junction bias current is provided by a second phase of the power source. NOR, NAND, 2NOR-OR and 2NAND-AND circuits are disclosed for use as building blocks in the production of specialized digital logic circuits.

Abstract: A multiple phase inductor includes a magnetic core having two end pieces and a plurality of legs extending between the end pieces to form flux paths which pass through the end pieces and the legs. Each leg includes a stack of "I" shaped laminations which are positioned between the end pieces to form two gaps in at least one of the flux paths. A coil is wound around each of the legs and all of the coils present substantially the same inductance to an external power circuit. By providing two gaps in each of the legs, localized heating of the turns of the coils is reduced.

Abstract: An apparatus for measuring cathodic protection voltage levels on a concealed conductive structure, includes a probe having a standard half cell reference electrode, a working electrode and an auxiliary electrode mounted in a fixed spacial relationship to each other, wherein the reference electrode, working electrode and auxiliary electrode are each in contact with an electrolytic solution. A voltage measuring device is provided for receiving a voltage from said reference electrode. The voltage measuring device provides an indication of the voltage difference between the reference electrode and a common reference point. A switch is included for connecting and disconnecting the working electrode with the common reference point. A voltage detecting circuit detects voltage between the concealed conductive structure, which is subject to a cathodic protection voltage, and the common reference point.

Abstract: A multiphased permanent magnet generator (PMG) driven by a rotating shaft, generates a multiphase output which is integrated and applied as the input to a high resolution phase locked loop having a binary counter with an output phase locked to the PMG multiphase output and representing shaft position. As applied to a high performance synchronous drive in which the PMG is driven by the synchronous machine, the digital shaft position signal is used to generate a multiphase current reference signal which is tracked by stator currents generated for the synchronous machine by a power current source. The multiphase current reference signal can be generated by a selected set of multiphase digital sine waveforms stored in a ROM which is part of the phase locked loop or is a separate waveform synthesizer.

Abstract: A liquid cooled electric generating apparatus is provided with a liquid circulation system that is divided into two portions. One of the portions includes a rotor mounted in a rotor cavity such that rotation of the rotor expels liquid from that portion of the circulation system. A normally open valve connects the two portions of the liquid circulation system. This valve is automatically closed during filling of the portion of the liquid circulation system which does not contain the rotor cavity. Both the liquid circulation system of the generating apparatus and the method of filling the system are encompassed by this invention.

Abstract: A superconducting sigma-delta analog-to-digital converter utilizes a superconducting inductor as the integrator and a Josephson junction connected in series between the inductor and ground as the quantizer. A SQUID generates sampling pulses at a selected GHz frequency which add to the inductor current flowing through the Josephson junction. When the combined current through the Josephson junction exceeds the critical current of the Josephson junction, a voltage pulse is generated which kicks back into the inductor to reduce the inductor current. The voltage across the Josephson junction is, therefore, a one bit digital representation of the analog signal. This one bit digital signal is converted to a multi-bit digital signal preferably by a decimator having superconducting circuits which reduce the frequency of the multi-bit digital signal to a frequency which can be further processed by semiconductor processors. Preferably, a weighting function is utilized in a conversion to improve accuracy.

Abstract: A method for automatically replenishing oil in a coolant system of an electric generator produces a first signal representative of the speed of the generator and a second signal representative of the pressure of oil in the coolant system of the generator. These signals are combined with a reference signal to produce a control signal representative of a low oil condition in the coolant system. When such low oil condition exists, additional oil is delivered to the coolant system in response to the control signal. In the preferred embodiment, this additional oil is supplied from a source of high pressure oil.

Abstract: An electric power system having line drop compensation includes a controllable electric power source having an output for supplying voltage to a power bus, a local voltage regulator for monitoring the output voltage of the power source and for producing a control signal representative of a desired nominal output voltage of the power source, and a remote voltage regulator for sensing voltage on the power bus at a point of regulation located away from the power source. The remote voltage regulator produces a pulse width modulated signal having a duty cycle representative of the voltage at the point of regulation. A pulse width to trim bias converter receives the pulse width modulated signal and produces the trim signal having a magnitude representative of the duty cycle of the pulse width modulated signal.

Abstract: Apparatus to extend the speed range and maximize torque of an ac drive by optimizing the torque angle as a function of speed. Using the back-emf of the machine, or the voltage from a permanent magnet generator mounted on the mtor shaft for reference, a novel analog biasing arrangement of a fast tracking multi-phase phase locked loop generates a set of stator current reference signals having a phase angle which is programmed to provide the optimum torque angle at any speed.

Abstract: An inverse time delay circuit includes an integrator for receiving a signal representative of a voltage or current in an external circuit and a reference signal. The integrator produces a control signal representative of the integral of the difference between the signals. A comparator compares the control signal to a second reference signal to produce an output which changes logic states when the magnitude of the control signals exceeds the magnitude of the second reference signal. A circuit is provided to control the magnitudes of one or both of the reference signals thereby providing control of the instantaneous and/or ultimate trip levels of the circuit.

Abstract: This is a structure of, and method for preparation of, molybdenum resistors in a superconductor integrated circuit. It utilizes a pattern superconductor film; applying a titanium film on the patterned superconductor film; and then applying a molybdenum film on the titanium film to provide a titanium-molybdenum, etch-stop interface; applying a patterned resist film on the molybdenum film; etching the exposed molybdenum film to expose a portion of the titanium-molybdenum, etch-stop interface; and oxidizing the exposed titanium-molybdenum, etch-stop interface. The titanium-molybdenum etch stop interface protects the patterned superconductor film and the support (including any other underlayers) and increases processing margins for the etch time.

Abstract: A method for modifying the frequency of a clock signal includes the steps of producing a clock signal having voltage pulses which occur at a first frequency and producing a control signal having voltage pulses which occur at a lower frequency. The frequency of the voltage pulses in the control signal is incremented in successive time intervals and the clock signal and control signal are combined such that one voltage pulse in the clock signal is deleted for each voltage pulse in the control signal. This results in a modified clock signal having a frequency which may be ramped up or down depending upon the initial frequency of the control signal and the direction in which the frequency of the control signal is incremented.

Abstract: A current fed unrestricted frequency converter (UFC) for supplying power with balanced voltages to a three-phase unbalanced load generates two sets of existence functions for controlling the switching matrices of the UFC to generate positive and negative sequence current components in the load. Existence function generators generating the positive and negative sequence existence functions are phase locked, respectively, to a positive sequence reference signal generated by a clock and a negative sequence reference signal derived by circuits which monitor the negative sequence voltage in the load. Select circuits alternately gate the positive and negative sequence existence functions to the UFC switching matrices in proportion to the detected magnitude of the negative sequence voltage in a sense to drive the negative sequence voltage in the load to zero.

Abstract: A differential protection circuit includes a pair of current transformers each having a secondary winding and each being inductively coupled to a power conductor at a different location. The secondary windings of these transformers are electrically connected in series with each other in a loop in a bucking arrangement. A resistor is connected in parallel with the secondary winding of each transformer. Control circuits are connected to sense a voltage signal appearing across the resistor and to take appropriate action when the sensed voltage reaches a predetermined level. An additional winding on one of the transformers provides isolation between the loop and one of the control circuits to prevent false tripping of the differential protection circuit.

Abstract: The widths of pulses in an incoming pulse train are monitored by successively measuring the duration of the pulses in the pulse train and enabling a timing device when the duration of any of the pulses is more than a preselected magnitude. The timing device is reset and restarted when the duration of any of the pulses is greater than the preselected magnitude. An output signal, indicative of an acceptable condition, is produced when the timing device indicates the expiration of a predetermined time delay. An output signal, indicative of a non-acceptable condition, is produced when the duration of a pulse in the incoming pulse train exceeds the preselected magnitude. This invention encompasses both the pulse width monitoring method and circuits which perform this method.