Abstract: A Galois field linear transformer includes a matrix responsive to a number of input bits in one or more bit streams and having a plurality of outputs providing the Galois field linear transformation of those bits; the matrix includes a plurality of cells, each cell including an exclusive OR logic circuit and AND logic circuit having an output connected to the exclusive OR logic circuit and an input connected to one of the input bits and a programmable storage device for providing an input to its associated AND logic circuit for setting the matrix to obtain a multi-cycle Galois field linear transformation of the inputs in a single cycle.

Abstract: A universal collection and transfer system which includes a collection container, a second container, and a transfer device mateable with both the collection container and the second container and including a hollow shaft which pierces the collection container to transfer a sample in the collection container into the second container.

Abstract: A calibrated current source includes current source having an output node; a calibration circuit; a load circuit; a cascode switching circuit including a pair of cascode switches, one connected between the local circuit and output node, the other connected between the calibration circuit and the output node; and a bias circuit selectively applying a bias voltage to the cascode switches to selectively connect the load circuit and the calibration circuit to the output node while maintaining a constant voltage at the output node and across the current source to provide a consistent current to the load and calibration circuits.

Abstract: A low quiescent power class AB current mirror circuit includes a first input transistor for receiving an input current and a second output transistor for providing an output current; the first and second transistors having bases connected together; and a first current supply for sinking current from the bases in response to a decrease in input current to lower the quiescent point of the transistors.

Abstract: An open-lattice, foldable, self-deployable structure with a number of spaced, bendable longitudinal members each having a curved cross section forming cells each bounded by a portion of two spaced longitudinal members and two spaced diagonal members. The diagonal members are joined to the longitudinal members at the cell boundary intersections of the diagonal members and the longitudinal members. The longitudinal members are made of a material which bends and flattens by a predetermined amount below the material's yield point and the diagonal members are made of a material which both bends and twists by a predetermined amount below the material's yield point so that the structure can be collapsed and then self resurrected.

Abstract: A method of manufacturing a dual load charge in a single consolidation pressing operation. A first type explosive is placed in a cavity to form a booster charge. A pocket is formed in the booster charge. A second type explosive is disposed in the pocket of the booster charge to form an initiating charge therein. Finally, the booster charge and the initiating charge are preferably simultaneously consolidated to form a dual load charge with intimate contact between the booster charge and the initiating charge. Also disclosed is a press useful for implementing the method of the invention.

Abstract: A method of anodically bonding a multilayer device with a free mass includes positioning a support layer on either side of a free mass structure including a free mass with an electrode on each layer proximate the free mass; connecting both electrodes and the free mass to a node at a floating potential and applying a voltage across the layers and free mass structure to bond at least one of the layers to the free mass structure.

Abstract: A method of equalizing total signal delay across a digital to analog interface includes constructing a plurality of unit digital to analog converter cells each having a clock input and a data input and an analog output; constructing an analog output network for summing the analog outputs for delivery to a termination which in combination with the analog output network defines a first predetermined time delay between the unit cells; constructing a clock input distribution network for propagating a clock input to each of the unit cells tapped along the clock input distribution network; and connecting a second termination to the clock input distribution network for establishing the clock input distribution network as a transmission line and defining in combination with the clock input distribution network a second predetermined time interval delay between the clock input to the unit cells equal to the first predetermined in the interval delay for synchronizing the propagation of the clock inputs propagating alon

Abstract: An interceptor missile including an infrared radiation detection subsystem and a window assembly in the hull of the missile optically coupled to the infrared radiation detection subsystem. The window assembly includes an inner window, an outer window, and a support subsystem between the inner and the outer windows defining a plurality of infrared transparent fluid flow cooling channels between the inner and outer windows. A source of fluid coupled to the cooling channels for cooling the outer window without adversely affecting the optical properties of either window.

Abstract: A non-contact vision based inspection system and method for flat specular parts in which an imaging camera defining an image plane is aimed at a part to be inspected for taking a single image of the part. A staging apparatus is used to move the part relative to the camera until the single image of the part is obtained. The image plane is fixed to remain parallel to the object plane defined by the part as the part moves relative to the imaging camera.

Abstract: A multi-phase, multi-access pipeline memory system includes a number, n, of processors; a pipeline memory including a latch; and a bus for interconnecting the processors and pipeline memory; a clock circuit responsive to a system clock signal divides the system clock signal into n phases for providing multiple clock signals corresponding to the n phases of the system clock signal for application to each processor to allow data and address to be transferred only during its assigned phase thereby enabling the memory and each processor to operate at the system clock rate while allowing n accesses to the memory during each system clock signal period, one access for each processor.