Patents Represented by Attorney Radlo & Su LLP
  • Patent number: 7970979
    Abstract: A high performance field programmable gate array is described with one or more signal processing engines coupled to a programmable logic fabric. Each signal processing engine includes a signal processing unit for performing specifying tasks and a bus-based configurable connection box for routing a bus-based input to a bus-based output. The signal processing unit has a floating point unit (FPU)/multiply accumulate (MAC) for computation and register files for storing information. The programmable logic fabric is coupled to the one or more signal processing engines for routing of information between the signal processing engines.
    Type: Grant
    Filed: September 19, 2007
    Date of Patent: June 28, 2011
    Assignee: Agate Logic, Inc.
    Inventors: Hare Krishna Verma, Manoj Gunwani, Ravi Sunkavalli
  • Patent number: 7944236
    Abstract: A bus structure providing pipelined busing of data between logic circuits and special-purpose circuits of an integrated circuit, the bus structure including a network of pipelined conductors, and connectors selectively joining the pipelined conductors between the special-purpose circuits, other pipelined connectors, and the logic circuits.
    Type: Grant
    Filed: August 12, 2010
    Date of Patent: May 17, 2011
    Assignee: Agate Logic, Inc.
    Inventors: Dana How, Godfrey P. D'Souza, Malcolm J. Wing, Colin N. Murphy, Arun Jangity
  • Patent number: 7940557
    Abstract: A configuration bit array including a hybrid electromechanical and semiconductor memory cell, and circuitry for addressing and controlling read, write, and erase accesses of the memory.
    Type: Grant
    Filed: December 21, 2010
    Date of Patent: May 10, 2011
    Assignee: Agate Logic, Inc.
    Inventors: David Richard Trossen, Malcolm John Wing
  • Patent number: 7902862
    Abstract: A bus structure providing pipelined busing of data between logic circuits and special-purpose circuits of an integrated circuit, the bus structure including a network of pipelined conductors, and connectors selectively joining the pipelined conductors between the special-purpose circuits, other pipelined connectors, and the logic circuits.
    Type: Grant
    Filed: September 14, 2007
    Date of Patent: March 8, 2011
    Assignee: Agate Logic, Inc.
    Inventors: Dana How, Godfrey P. D'Souza, Malcolm J. Wing, Colin N. Murphy, Arun Jangity
  • Patent number: 7885103
    Abstract: A configuration bit array including a hybrid electromechanical and semiconductor memory cell, and circuitry for addressing and controlling read, write, and erase accesses of the memory.
    Type: Grant
    Filed: November 22, 2005
    Date of Patent: February 8, 2011
    Assignee: Agate Logic, Inc.
    Inventors: David Richard Trossen, Malcolm John Wing
  • Patent number: 7873376
    Abstract: A method and system are disclosed in which a Mobile Terminated SMS (Short Message Service) wireless message generated by a Computer Application containing an embedded response menu can be sent to a Mobile Handset and in which a Mobile Originated response from the Mobile Handset can be uniquely re-associated with the original Mobile Terminated message is described. Given that SMS provides no inherent association between Mobile Terminated and Mobile Originated messages, the method and system provide a scheme in which the original Computer Application menu response options are remapped to unique values prior to delivery to the Mobile Handset. When the response is received from the Mobile Handset, the method can uniquely re-associate and reverse map the response code back to the original Mobile Terminated message and original menu response options.
    Type: Grant
    Filed: February 18, 2010
    Date of Patent: January 18, 2011
    Assignee: iTechTool Incorporated
    Inventor: David R. Coelho
  • Patent number: 7836113
    Abstract: A dedicated logic cell in a programmable logic structure is described that comprises the following primary components: a configurable logic function or look-up table (LL), a dedicated logic function (DL), a sequential logic function (LS), and a control logic function (LC). In this illustration, the dedicated logic cell comprises two configurable logic functions, two sequential logic functions, a dedicate logic function, and a control logic function. In a first embodiment, the dedicated logic cell is constructed with a combination of configurable logic functions that are coupled to a dedicated logic function in order to perform a four 2-input function, an AND function, an OR function, or an XOR function. In a second embodiment, the dedicated logic cell is constructed with a combination of configurable logic functions that are coupled to a dedicated logic function in order to perform a four 2-to-1 multiplexer function.
    Type: Grant
    Filed: October 9, 2006
    Date of Patent: November 16, 2010
    Assignee: Agate Logic, Inc.
    Inventors: Ravi Sunkavalli, Hare K. Verma, Manoj Gunwani, Elliott Delaye
  • Patent number: 7814136
    Abstract: A programmable system is disclosed having multiple configurable floating point units (“FPU”) that are coupled to multiple programmable logic and routing blocks and multiple memories. Each floating point unit has static configuration blocks and dynamic configuration blocks, where the dynamic configuration blocks can be reconfigured to perform a different floating point unit function. A floating point unit includes a pre-normalization for shifting an exponent calculation as well as shifting and aligning a mantissa, and a post-normalization for normalizing and rounding a received input. The post-normalization receives an input Z and realigns the input, normalizes the input and rounds the input Z.
    Type: Grant
    Filed: February 1, 2006
    Date of Patent: October 12, 2010
    Assignee: Agate Logic, Inc.
    Inventors: Hare K. Verma, Ravi Sunkavalli, Manoj Gunwani
  • Patent number: 7757193
    Abstract: A method for clustering logic units in a field programmable integrated chip to generate a set of clusters is disclosed. The clustering step for forming a super cluster comprises a first logic element and a second logic unit a first logic unit and a super cluster, or a first super cluster and a second super cluster. The method includes generating all possible configurations by enumerating all possible two-way relationships combining a driver-and-receiver relationship from a pool of a finite number of dedicated connections. The set of all possible configurations is reduced to a subset of configurations based on one or more multi-dimension criteria. Each dimension in the multi-dimensional criteria is represented by a parameter. The method involves prioritizing a collection of parameters so that a set of selected parameters or a set of selected criteria is used to generate a desirable number of subsets of configurations.
    Type: Grant
    Filed: October 2, 2006
    Date of Patent: July 13, 2010
    Assignee: Agate Logic, Inc.
    Inventor: Bo Hu
  • Patent number: 7728623
    Abstract: A programmable logic structure is disclosed employing input logic routing cell (ILRC) multiplexers and output logic routing cell (OLRC) multiplexers for making local connections between dedicated logic cells. In a simple programmable logic structure, a dedicated logic cell (DLC) is implemented in a programmable logic structure comprising multiple ILRC multiplexers for port A and multiple OLRC multiplexers for port B. In a multi-level programmable logic structure, multiple columns of dedicated logic cells is designed with columns of dedicated local cells adjacent to each other where each DLC column is used to implement a particular logic function. In a first embodiment, local connections can be made between dedicated logic cells, e.g. an OLRC in a first DLC at level L making local point-to-point connections to an ILRC in a second DLC at level L+1.
    Type: Grant
    Filed: October 9, 2006
    Date of Patent: June 1, 2010
    Assignee: Agate Logic, Inc.
    Inventors: Hare K. Verma, Ravi Sunkavalli, Sudip Nag, Conrad Kong, Bo Hu, Chandra Mulpuri, Ashok Vittal
  • Patent number: 7716330
    Abstract: An apparatus for controlling transmission of data packets in an information network comprises a Regional Transaction Processor (RTP) operable to communicate with a Data Enabling Device (DED) and at least one workstation. The DED searches data packets for content match information. The RTP includes instructions to generate information to include in a prompt to be presented at the workstation when the content match information is detected in at least one of the data packets. The prompt is based on information in the data packet. Transmission of the data packets through the information network is suspended by the DED until a response to the prompt is received that authorizes downloading the data packets to the workstation. If transmission of the data packets to the workstation is not authorized, the data packets are discarded by the DED.
    Type: Grant
    Filed: October 19, 2001
    Date of Patent: May 11, 2010
    Assignee: Global Velocity, Inc.
    Inventors: Matthew P. Kulig, Timmy L. Brooks, John W. Lockwood, David Kyle Reddick
  • Patent number: 7711844
    Abstract: A method for obtaining data while facilitating keeping a minimum amount of state is provided. The method includes receiving at a first device an Internet Protocol (IP) frame sent from a second device to a third device wherein the first device is in a flow path between the second and third devices, the first device including at least one of an Application Specific Integrated Circuit (ASIC) and a Field Programmable Gate Array FPGA. The method also includes removing an embedded stream-oriented protocol frame including a header and a data packet from the received IP frame with at least one of the ASIC and the FPGA, and determining a validity of a checksum of the removed steam-oriented protocol header.
    Type: Grant
    Filed: August 15, 2002
    Date of Patent: May 4, 2010
    Assignee: Washington University of St. Louis
    Inventors: David V. Schuehler, John W. Lockwood
  • Patent number: 7676235
    Abstract: A method and system are disclosed in which a Mobile Terminated SMS (Short Message Service) wireless message generated by a Computer Application containing an embedded response menu can be sent to a Mobile Handset and in which a Mobile Originated response from the Mobile Handset can be uniquely re-associated with the original Mobile Terminated message is described. Given that SMS provides no inherent association between Mobile Terminated and Mobile Originated messages, the method and system provide a scheme in which the original Computer Application menu response options are remapped to unique values prior to delivery to the Mobile Handset. When the response is received from the Mobile Handset, the method can uniquely re-associate and reverse map the response code back to the original Mobile Terminated message and original menu response options.
    Type: Grant
    Filed: August 9, 2006
    Date of Patent: March 9, 2010
    Assignee: iTechTool Incorporated
    Inventor: David R. Coelho