Abstract: A process for forming defect-free source and drain extensions for a MOSFET built on a germanium based channel region deposits a first silicon germanium layer on a semiconductor substrate, deposits a gate dielectric layer on the silicon germanium layer, and deposits a gate electrode layer on the gate dielectric layer. A dry etch chemistry etches those layers to form a gate electrode, a gate dielectric, and a silicon germanium channel region on the semiconductor substrate. Next, an ion implantation process forms halo implant regions that consume portions of the silicon germanium channel region and the semiconductor substrate. Finally, an in-situ doped epitaxial deposition process grows a pair of silicon germanium layers having LDD regions. The silicon germanium layers are adjacent to the silicon germanium channel region and the halo implant regions do not damage any portion of the silicon germanium layers.

Abstract: A method of forming a transistor gate stack having an annealed gate dielectric layer begins by providing a substrate that includes a first and second spacer separated by a trench. A conformal high-k gate dielectric layer is deposited on the substrate and within the trench with a thickness that ranges from 3 ? to 60 ?. Next, a capping layer is deposited on the high-k gate dielectric layer that substantially fills the trench and covers the high-k gate dielectric layer. The high-k gate dielectric layer is then annealed at a temperature that is greater than or equal to 600° C. The capping layer is removed to expose an annealed high-k gate dielectric layer. A metal layer is then deposited on the annealed high-k gate dielectric layer. A CMP process may be used to remove excess material and complete formation of the transistor gate stack.

Abstract: Embodiments of the invention provide a device with a multiple gates. Stress material within recesses of a device body metal gate may cause a stress in channel regions of the device, thereby improving performance of the device.