Abstract: An exemplary apparatus is disclosed that comprises a plurality of voltage to current transducers to convert an input signal voltage into a plurality of input signal currents and a cascode stage. The cascode stage is coupled to the voltage to current transducers to provide amplifier gain control. The cascode stage comprises a thin gate oxide transistor and a thick gate oxide transistor.

Abstract: Exemplary embodiments are directed to broadcasting data on a USB system. The system includes a USB host and multiple broadcast-capable USB devices. Each USB device includes at least a default control endpoint for receiving control information and an isochronous sink endpoint for receiving a broadcast stream. The USB host programs a shared device address to an address register of each USB device such that all broadcast-capable USB devices programmed to that shared device address will accept the broadcast stream. One of the USB devices at the shared device address is set as a primary broadcast slave that will respond to non-isochronous transfers to the shared device address. All other USB devices with the shared device address are set to secondary slaves that ignore non-isochronous transfers to the shared device address.

Abstract: Short-circuit protection in switched output stages is described to protect switching output stages from excessive output current in short-circuit conditions which may cause device damage. Design techniques to attain this goal include measuring currents in switching transistors by placing a scaled transistor in parallel thereto, combined with circuitry for making drain voltages substantially equal. The various techniques for short-circuit protection comprise (a) using a transistor and an operational amplifier in combination, (b) using a single transistor in place of the operational amplifier, (c) using a circuit to generate over-current detection signals, (d) providing over-current detection signals to a driver in order to reduce the output current, (e) using an inverter to feedback regulate output current, (f) using a switch to bypass the current regulator during normal operation, and (g) automatically opening this switch in an over-current situation.

Abstract: Amplifiers with improved linearity and noise performance are described. In an exemplary design, an apparatus includes first through sixth transistors. The first transistor receives an input signal and provides an amplified signal. The second transistor receives the amplified signal and provides signal drive for an output signal. The third transistor receives the input signal and provides an intermediate signal. The fourth transistor provides bias for the third transistor in a high linearity mode. The fifth transistor receives the intermediate signal and provides signal drive for the output signal in a low linearity mode. The third and fourth transistors form a deboost path that is enabled in the high linearity mode to improve linearity. The third and fifth transistors form a cascode path that is enabled in the low linearity mode to improve gain and noise performance. The sixth transistor generates distortion component used to cancel distortion component from the first transistor.

Abstract: A differential Low Noise Amplifier (LNA) includes a first stage of resistive feedback amplifiers and second stage of complementary amplifiers, where the outputs of the first stage are coupled to the inputs of the second stage in a cross-coupled fashion. An inductive load, such as a transformer, combines signals output from the complementary amplifiers of the second stage. In one example, the LNA has an input impedance of less than 75 ohms, a noise factor of less than 2 dB, and a gain of more than 20 dB. Due to the low input impedance, the LNA is usable to amplify a signal received from a source having a similar low impedance without the use of an impedance matching network between the output of the source and the input of the LNA.

Abstract: A high linear fast peak detector having a variable bias current and/or a variable bias voltage is described. In an exemplary design, the peak detector includes a transistor, a variable current source, a capacitor, and a feedback circuit. The transistor receives the input signal and provides a source current. The variable current source receives the input signal, provides high bias current when the input signal is low, and provides low bias current when the input signal is high. The capacitor is charged by the source current when the input signal is high and is discharged by the high bias current when the input signal is low. The feedback circuit receives a detected signal from the capacitor and provides higher bias voltage for the transistor when the input signal is high, which results in higher source current from the transistor.

Abstract: Techniques for providing a comparator incorporating amplitude hysteresis. In an exemplary embodiment, a current offset stage is coupled to a comparator having a folded cascode architecture. The current offset stage offsets the current generated from an input stage to delay switching of the comparator output to implement amplitude hysteresis. In an exemplary embodiment, rail-to-rail input voltages may be accommodated by providing dual NMOS and PMOS input stages. In another exemplary embodiment, the amplitude hysteresis may be controlled by an adjustable threshold voltage. In yet another exemplary embodiment, a constant transconductance gm bias circuit may be provided to maintain the stability of the threshold voltage across input common-mode voltage and/or other variations.

Abstract: A wideband antenna, for use in portable computers incorporating at least one wireless communication device, with improved radiated antenna efficiency across a broad range of operating frequency bands with minimal additional physical size or cost, is described. In an exemplary embodiment, the wideband antenna is defined by at least a first and second housing, where a first metal structure in at least a first one of the at least a first and second housings is commonly connected to at least two antenna RF feed ports at a boundary of the at least a first and second housing. In a further exemplary embodiment, the device is a portable computer, and the first housing is an upper display housing, the second housing includes a wireless communication device with at least two RF signal paths to at least two antenna RF feed ports, and the second housing further includes a second metal structure commonly connected to at least two antenna RF feed ports of the wideband antenna.

Abstract: An apparatus includes first and second filters and a bandwidth control circuit. The first filter operates as part of a first oscillator in a first mode and filters a first input signal and provides a first output signal in a second mode. The second filter operates as part of a second oscillator in the first mode and filters a second input signal and provides a second output signal in the second mode. The bandwidth control circuit adjusts the bandwidth of the first and second filters in the first mode, e.g., adjusts the oscillation frequency of each oscillator to obtain a target bandwidth for an associated filter. The apparatus may further include first and second gain control circuits. Each gain control circuit may vary the amplitude of an oscillator signal from an associated oscillator and/or set a gain of an associated filter in the first mode.

Abstract: Level shifters and high voltage logic circuits implemented with MOS transistors having a low breakdown voltage relative to the voltage swing of the input and output signals are described. In an exemplary design, a level shifter includes a driver circuit and a latch. The driver circuit receives an input signal having a first voltage range and provides a drive signal having a second voltage range. The first and second voltage ranges may cover positive and negative voltages or different ranges of positive voltages. The latch receives the drive signal and provides an output signal having the second voltage range. The driver circuit may generate a control signal having a full voltage range based on the input signal and may then generate the drive signal based on the control signal. The level shifter may be used to implement a high voltage logic circuit.

Abstract: Techniques for optimizing the power consumption of existing low cost multi-gain state power amplifiers (PA) to increase the talk time of wireless communication devices are described. In an exemplary embodiment a device, such as a baseband processor, operates to set a multistage PA having at least two gain states for amplifying a transmit signal to a lowest power consuming gain state. The device calculates a transition power level as a function of an identified maximum power reduction (MPR) value and switches the PA to a higher gain state from a lower gain state when a transmission power level is higher than the calculated transition power level.

Abstract: A receiver with a balanced I/Q transformer is described. In an exemplary design, the receiver includes an LNA that amplifies a received RF signal and provides a single-ended RF signal to the balanced I/Q transformer. The balanced I/Q transformer includes at least one primary coil and first and second secondary coils. The first secondary coil is magnetically coupled to the at least one primary coil and provides a first differential RF signal to a first mixer. The second secondary coil is magnetically coupled to the at least one primary coil and provides a second differential RF signal to a second mixer. The first and second mixers downconvert the first and second differential RF signals with I and Q LO signals, respectively, and provide differential I and Q downconverted signals. The primary and secondary coils may be fabricated on two conductive layers of an integrated circuit.

Abstract: A resonator of a VCO includes a fine tuning main varactor circuit, an auxiliary varactor circuit, and a coarse tuning capacitor bank circuit coupled in parallel with an inductance. The main varactor circuit includes a plurality of circuit portions that can be separately disabled. Within each circuit portion is a multiplexing circuit that supplies a selectable one of either a fine tuning control signal (FTAVCS) or a temperature compensation control signal (TCAVCS) onto a varactor control node within the circuit portion. If the circuit portion is enabled then the FTAVCS is supplied onto the control node so that the circuit portion is used for fine tuning. If the circuit portion is disabled then the TCAVCS is supplied onto the control node so that the circuit portion is used to combat VCO frequency drift as a function of temperature. How the voltage of the TCAVCS varies with temperature is digitally programmable.

Abstract: A mobile station with a tunable duplexer is disclosed. The mobile station includes a processor and memory in electronic communication with the processor. The mobile station includes a receive path that has a receive band reject filter in electronic communication with an antenna at a common node. The receive path also includes a receive band pass filter in electronic communication with the receive band reject filter. The mobile station includes a transmit path that has a transmit band reject filter in electronic communication with the antenna at the common node. The transmit path also includes a transmit band pass filter in electronic communication with the transmit band reject filter.

Abstract: A low noise amplifier (LNA) with combined input matching, balun, and/or transmit/receive (T/R) switch is described. In one exemplary design, an apparatus includes a coupled inductor and an LNA. The coupled inductor receives a single-ended input signal, performs single-ended to differential conversion, and provides a differential input signal. The LNA receives and amplifies the differential input signal and provides a differential output signal. The coupled inductor includes magnetically coupled first and second coils. The first coil provides input impedance matching when the LNA is enabled. A resonator circuit formed with the first coil provides high input impedance when the LNA is disabled. A tuning capacitor coupled to the second coil provides amplitude imbalance tuning for the differential input signal. A transmit switch is coupled between the first coil and a transmitter.

Abstract: Techniques for generating quadrature signals from a local oscillator signal, wherein the generated quadrature signals have a frequency half of the local oscillator frequency. In an exemplary embodiment, two oscillators, e.g., injection locked oscillators, are provided, each oscillator having a load, a cross-coupled transistor pair, an integrating capacitor, and current injection transistors. A differential pair is coupled to the leads of each of the integrating capacitors, and the drains of the differential pair are coupled to the outputs of the other oscillator to help increase the slew rate of the output voltages of the other oscillator. The inputs to the differential pair may be first amplified to improve the gain of the differential pair. In another exemplary embodiment, the power consumption of the differential pair may be reduced by operating them in a discontinuous mode, e.g., by coupling the source voltages of the differential pair to corresponding delayed versions of the drain voltages.

Abstract: Disclosed are circuits, techniques and methods for buffering a high frequency signal for transmission over an integrated circuit. In one particular implementation, a plurality of amplification circuits are individually biased for amplifying a signal from a voltage controlled oscillator and/or digitally controlled oscillator to provide a local oscillator signal on a device.

Abstract: An amplifier (e.g., an LNA) with improved ESD protection circuitry is described. In one exemplary design, the amplifier includes a transistor, an inductor, and a clamp circuit. The transistor has a gate coupled to a pad and provides signal amplification for the amplifier. The inductor is coupled to a source of the transistor and provides source degeneration for the transistor. The clamp circuit is coupled between the gate and source of the transistor and provides ESD protection for the transistor. The clamp circuit may include at least one diode coupled between the gate and source of the transistor. The clamp circuit conducts current through the inductor to generate a voltage drop across the inductor when a large voltage pulse is applied to the pad. The gate-to-source voltage (Vgs) of the transistor is reduced by the voltage drop across the inductor, which may improve the reliability of the transistor.

Abstract: Method and apparatus for automatically controlling the operation of a DC power enhancement circuitry connected to an RF power amplifier (PA) that operates at various input signal levels, according to which the instantaneous magnitude of the input signal is sensed and the instantaneous magnitude and its highest (lowest) peak are stored. For the time period during which the peak remains the highest (lowest) peak, the desired dynamic range of the power amplifier is determined according to the peak and a corresponding threshold level and the gain of the enhancement circuitry are determined according for that time period. Whenever the magnitude exceeds the corresponding threshold level, the enhancement circuitry provides to the power amplifier a level of DC power enhancement required for maintaining the output power of the power amplifier within the output dynamic range.

Abstract: Techniques for designing a switchable amplifier are described. In one aspect, a switchable amplifier including a core amplifier circuit configured to selectively enable one or more parallel input transistor pairs is described. The core amplifier circuit comprises a permanently enabled input transistor pair. In another aspect, a device operable between a first mode of operation and a second mode of operation comprising a receiver logic circuit for selectably enabling and disabling a plurality of input transistor pairs within a switchable amplifier is described where the switchable amplifier also includes a core amplifier circuit coupled to the receiver logic circuit for selectably enabling and disabling a transistor pair therein. The described switchable amplifiers result in the ability to provide varying amplifier performance characteristics based upon the current mode of operation of the device.