Abstract: Setting information is transferred to an information processing apparatus from another information processing apparatus. The information processing apparatus includes a transfer unit, a rule unit, an acquiring unit, and an updating unit. The transfer unit sets transfer instruction information to instruct a transfer process to be performed, when the user logs in and while an administrator is logged in. The rule unit sets up an operating environment for the user based on rule setting information in a case when the user logs into the information processing apparatus for the first time. The acquisition unit acquires setting information of the user from a transfer file where the setting information acquired from the other information processing apparatus as a transfer source is stored while the user is logged in, where the transfer instruction information has been set. The updating unit updates the rule setting information with the acquired setting information.

Abstract: A system for controlling I/O transfers includes a host system or initiator including an adapter driver layer; and a storage controller. The storage controller includes a priority store and an operation queue. The adapter driver is selectively responsive to a datapath command from an initiator application for setting a default I/O priority for a specified logical unit, for storing the default I/O priority for the logical unit to a priority store of the storage controller, and selectively responsive to a data transfer command from an initiator application for storing the data transfer command to the storage controller. The storage controller is responsive to the datapath command for storing the I/O priority default value for the logical unit to the priority store; and responsive to the data transfer command with respect to the logical unit for queuing the data transfer command for execution based on the I/O priority default value.

Abstract: A test system for a heterogeneous multipath network. A tester system evaluates a plurality of status indicators from a plurality of types of test components in a network. Based on the status indicators of at least one of the test components, the tester system selects a first test to be performed. After executing the first test, the tester system selects a second test to be performed based on the status indicators of at least one of the test components and a result of the first test.

Abstract: To evaluate a communications network, a plurality of network evaluation signals, or probative test packets, are selectively sent and received through the network. Responsive to these evaluation signals, network evaluation parameters are determined and stored. Queuing theory analysis, responsive to these parameters, determines the response time and throughput characteristics, including discrete capacity, utilization and performance, of the network. Calculation of the value of the network's discrete utilization involves the measurement of the network's average delay waiting for service, measurement of the network's standard deviation of delay waiting for service, calculation of discrete utilization from the ratio of these observed values, and then refinement of that calculation by proportionate factoring in instances of dropped samples as cases of one hundred percent utilization to arrive at a final figure for percent of network discrete utilization.

Abstract: Challenge-response and probative methods together or independent of each other enable detection of devices participating in denial of service (DOS) and distributed DOS (DDOS) attacks upon a network resource, and upon identification of devices participating in attacks, minimize the effect of the attack and/or minimize the ability of the device to continue its attack by placing the attacking devices in a state of reduced or denied service.

Abstract: In one form, in a method for mapping file handles, protocol data elements are created for respective file system protocols. Such a protocol data element identifies a structure of server handles for the data element's corresponding protocol. File system data elements are created for server file systems. Such a file system data element includes a file system identification (FSID) attribute. Responsive to accessing an object of one of the server file systems, a value for the FSID attribute of the corresponding file system data element is created for reconstructing the object's server handle. Creating the value includes parsing, responsive to one of the protocol data elements, an FSID of a server handle for the object.

Abstract: In one form, in a method for making file systems accessible, a referring file system attribute is created, responsive to a first file system having a referral object referring to a second file system. The referring file system attribute describes referring file system identification for the first file system. A path attribute is created, responsive to the first file system having the referral object, describing a path from a root of the first file system to the referral object. A referred file system attribute is created, responsive to the first file system having the referral object, describing a referred file system identification for the second file system. A parent attribute is created, responsive to the first file system having the referral object, describing a parent flag for the second file system.

Abstract: A system and method for determining the physical location of a target device. Using communications network trace route and pinging commands, the distances of three test devices of known locations to the target device are determined; and responsive to those distances, the location of the target device is determined by triangulation. Based upon location, the target device may be blocked from a communications network or connected to a particular server.

Abstract: A method and system for detecting a failure in a dynamic random access memory (DRAM) array having a plurality of cells organized in a matrix fashion of rows and columns. The method includes reading the content of a first row of cells of the memory array during a first refresh cycle. After obtaining the content from the first row of cells, a first complement of the content is generated. The generated first complement is then written back to the first row of cells during the writeback operation of the first refresh cycle. During the subsequent refresh cycle, the first complement in the first row of cells is read and a second complement of the first complement is generated. Next, the original content in the first row of cells is compared with the second complement. In response to the original content not being equal to the second complement, a control signal is generated to indicate a failure in the memory array.

Abstract: The invention relates to an enclosure comprising a housing and a device connecting card which is compliantly connected within the housing. The compliant connection, in use, disperses mounting stresses caused by a device in the housing.

Abstract: A fault tolerant memory system and method of operation thereof. The fault tolerant memory system includes a number of memory arrays including at least one spare memory array, wherein each of the memory arrays has an internal error detection circuit. In an advantageous embodiment, the internal error detection circuit includes an inverter, a register coupled to the inverter and a comparator for comparing the contents of the inverter and register. The comparator will generate an error signal to indicate a failed memory array in response to the contents of the inverter and register not being equal. The fault tolerant memory system also includes data correction logic that corrects data stored in a failed memory array and, in an advantageous embodiment, restores “corrupted” data in a failed array by reading the content of a row of cells in the failed memory array and generating a first complement of the content.

Abstract: A method for providing a fault tolerant memory system having a number of memory arrays that includes at least one spare memory array and utilizing a data word organization of greater than 4 bits. The method includes detecting a multi-bit word error in a memory array. In an advantageous embodiment, a single package detect (SPD) logic, for detecting a package error of 1-4 bits, is utilized to identify the failed memory array. Next, the content of a first row of cells in the failed memory array is read and a first complement of the content is generated. Subsequently, the first complement is written back to the first row of cells in the failed array. A second read operation is then initiated to retrieve the first complement from the failed memory array, following which, a second complement of the first complement is generated. The second complement is then written to a corresponding first row of cells in the spare memory array and the method is repeated for all row of cells in the failed memory array.

Abstract: A method and arrangement are described for decompressing three or more bytes per processor cycle from a stream of compressed data using a processing pipeline, in which the compressed data is represented by tokens of varying and unknown length by accepting as input the stream of token data, partially decoding a token from the token data to determine a boundary position of the token; and priming the processing pipeline with the token and a length marker indicating the boundary position. Literal data is detected and output directly, copy pointers are checked to find their targets and resolved either from the history buffer or from the in-process contents of the pipeline.

Abstract: This invention relates to apparatus and a method for connecting a pin array and a circuit board. In particular, the invention relates to pin array connections used in connecting disk drives into disk drive enclosures. Connection is accomplished by using a multi-pinned plug connector which sequentially engages conductive surfaces at different levels within the receiving PCB. The plug connector is connected electrically at its opposing end to a second PCB.

Abstract: An on-chip diagnostic system is used with an internal bus (10) of an integrated circuit. The bus has a number of byte-wide data lanes. A register (20) of the system is arranged to store a byte pattern. A series of comparators (30) receive byte signals from each of the byte lanes of the internal bus (10) and compare these with the byte pattern from the register (20). Outputs from the comparators are provided to a decoder (40) which provides, in the case of one of the byte lanes containing the same byte as the data pattern, an output signal (50) identifying that data lane, to a diagnostic port of the integrated circuit. In this way more information may be provided at the diagnostic port at any one time. An entire internal bus may be monitored in a single test run whilst at the same time making more of the diagnostic port available for tracing control signals, thus reducing the amount of time required to determine the cause of chip design problems.

Abstract: A secondary servo actuator system for use in disk drives comprising a controller and two PZT transducers mounted on each suspension load beam in an arm assembly. When a seek operation is initiated the acceleration of the arms generates vibration modes. The PZT transducers on a suspension adjacent to the target head/suspension sense the vibration motion and provide output signals to the controller. The controller filters the signal and generates a control signal for the PZTs mounted on the target arm/suspension. The deformation of the PZTs in turn rotates the arm load beam and thereby adjusts the position of the target head to compensate for arm motion caused by the vibration modes. The secondary actuator system can be used during the deceleration trajectory of a target head to suppress lower order arm sway frequencies.

Abstract: The invention relates to a method for writing servo patterns on a data recording disk of a disk drive device. A read/write head is stopped at a reference position on the data recording disk, then the read/write head is moved along a radial direction of the data recording disk from the reference position, then a determination is made as to whether the data recording disk has a sufficient width along the radial direction to write a predetermined number of servo tracks, or not, then the servo patterns are written on the servo tracks if the data recording a disk has the sufficient width.

Abstract: A system and method for adaptively compensating for real-time variations in mechanical dynamics of a head-positioning assembly during track follow and seek operations. The head-positioning assembly includes a voice coil actuator that positions a read/write head utilizing a coil and carriage in conformity with an actuator control signal. Variations in resonant mode characteristics are anticipated in real-time in accordance with measured temperature variations. These parametric variations are translated in real-time by a state space model to determine a secondary velocity and displacement of the read/write head during track follow and seek operations. In response to this secondary velocity and displacement determination, the actuator control signal is dynamically adjusted to compensate for the determined secondary head velocity and displacement, thereby improving head positioning accuracy and increasing servo bandwidth.