Abstract: A switched capacitor circuit for use at at least one operating frequency is provided. The switched capacitor may include an inductive element having a first terminal coupled to a switching voltage and a second terminal. The switched capacitor circuit may further include a hetero-junction bipolar transistor (HBT) having a base terminal coupled to the second terminal of the inductive element, a first conducting terminal, and a second conducting terminal coupled to a voltage supply terminal.

Abstract: A device (45) receives new program files (46) and uses pre-internalized images to avoid having to internalize a program file every time that program execution occurs. In one embodiment, a software Virtual Machine (50) in the device functions to implement the pre-internalization. Once the program files are pre-internalized to create images that are stored in a permanent memory (56) of the device, the images may subsequently be executed without having to perform a pre-internalization operation. Additionally, use of dynamic memory (52) is reduced in connection with subsequent program execution and execution time of new program files is reduced.

Abstract: A first packaged integrated circuit (IC) includes a package substrate, at least one IC die attached to a first surface of the package substrate, a plurality of conductive members on the first surface at least partially surrounding the at least one IC die and electrically connected to the at least one IC die, an encapsulant over the first surface surrounding the at least one IC die and the plurality of conductive members, wherein at least a portion of each of the plurality of conductive members is exposed by the encapsulant. A second packaged IC may be stacked onto the first packaged IC. The second packaged IC includes at least one IC die and a plurality of conductive members, each conductive member of the plurality of conductive members of the second packaged IC is in contact with a corresponding conductive member of the plurality conductive members of the first packaged IC.

Abstract: A method including providing a substrate and providing an insulating layer overlying the substrate is provided. The method further includes providing a body region comprising a body material overlying the insulating layer. The method further includes forming at least one transistor overlying the insulating layer, the at least one transistor having a source, a drain and a gate with a sidewall spacer, the sidewall spacer comprising a substantially uniform geometric shape around the gate, the gate overlying the body region. The method further includes forming a first silicide region within the source and a second silicide region within the drain, the first silicide region having a differing geometric shape than the second silicide region and being electrically conductive between the body region and the source.

Abstract: A data processing system includes a processor having a multi-way cache which has a first and a second way. The second way is configurable to either be redundant to the first way or to operate as an associative way independent of the first way. The system may further include a memory, where the processor, in response to a read address missing in the cache, provides the read address to the memory. The second way may be dynamically configured to be redundant to the first way during operation of the processor in response to an error detection signal. In one aspect, when the second way is configured to be redundant, in response to the read address hitting in the cache, data addressed by an index portion of the read address is provided from both the first and second way and compared to each other to determine if a comparison error exists.

Abstract: A data processing system may comprise an initiator device having an output whose timing is referenced by a clock input alone corresponding to a first delay along a signaling path. The exemplary data processing system further may further comprise a target device having an input whose timing is referenced by a clock input alone corresponding to a second delay along the signaling path and a system bus interconnected between the initiator device and the target device within the signaling path. The exemplary data processing system may further comprise a dynamic timing bridge coupled to the system bus within the signaling path, wherein responsive to a control signal representative of at least one system characteristic, the dynamic timing bridge performs one selected from the group consisting of (i) inserting a cyclic latency within the signaling path and (ii) not inserting the cyclic latency within the signaling path.

Abstract: A method of operating a bus interconnect coupled to bus masters and bus slaves is provided. The method includes receiving a request from a bus master to perform a bus transaction associated with a transaction ID with a bus slave of the plurality of bus slaves, the bus transaction being a first type of bus transaction. The method further includes performing the transaction if a resource allocation parameter allocated to the bus master meets a first threshold. The method further includes if the resource allocation parameter does not meet the first threshold, performing the data transaction only if the transaction meets a condition of a set of at least one condition, wherein a condition of the set of at least one condition includes that the transaction ID of the transaction is not a transaction ID of any outstanding bus transaction of the first type requested by the bus master.

Abstract: A portion of a memory may include a first memory block, including a first memory cell coupled to a first memory data line, a second memory block, including a second memory cell coupled to a second memory data line, and a latch, having a first terminal and a second terminal. The portion of the memory may further include a first N-channel transistor, having a first current electrode coupled to the first terminal of the latch, having a second current electrode coupled to a first power supply voltage, and having a control electrode coupled to the first memory data line. The portion of the memory may further include a second N-channel transistor, having a first current electrode coupled to the first terminal of the latch, having a second current electrode coupled to the first power supply voltage, and having a control electrode coupled to the second memory data line.

Abstract: A memory (10) has a plurality of memory cells, a serial address port (47) for receiving a low voltage high frequency differential address signal, and a serial input/output data port (52, 54) for receiving a high frequency low voltage differential data signal. The memory (10) can operate in one of two different modes, a normal mode and a cache line mode. In cache line mode, the memory can access an entire cache line from a single address. A fully hidden refresh mode allows for timely refresh operations while operating in cache line mode. Data is stored in the memory array (14) by interleaving in multiple sub-arrays (15, 17). During a hidden refresh mode of operation, one sub-array (15) is accessed while another sub-array (17) is refreshed. Two or more of the memories (10) may be chained together to provide a high speed low power memory system.

Abstract: A semiconductor fabrication process includes patterning a hard mask over a semiconductor substrate to expose an isolation region and forming a trench in the isolation region. A flowable dielectric is deposited in the trench to partially fill the trench and a capping dielectric is deposited overlying the first oxide to fill the trench. The substrate may be a silicon on insulator (SOI) substrate including a buried oxide (BOX) layer and the trench may extend partially into the BOX layer. The flowable dielectric may be a spin deposited flowable oxide or a CVD BPSG oxide. The flowable dielectric isolation structure provides a buffer that prevents stress induced on one side of the isolation structure from creating stress on the other side of the structure. Thus, for example, compressive stress created by forming silicon germanium on silicon in PMOS regions does not create compressive stress in NMOS regions.

Abstract: A method for accessing a memory comprising a first set of bit columns, a second set of bit columns, and a redundant set of bit columns, wherein any one of the redundant set of bit columns can be substituted for one of the first set of bit columns or one of the second set of bit columns and wherein each of the bit columns can receive a read voltage or a write voltage, is provided. The method includes during a write operation to the first set of bit columns, providing the write voltage to one of the redundant set of bit columns, if the one of the redundant set of bit columns has been substituted for one of the first set of bit columns, otherwise providing the read voltage to the redundant set of bit columns.

Abstract: A memory has a first memory block, a second memory block, a data bus, a first sense amplifier, a second sense amplifier, a first circuit, and a second circuit. The first sense amplifier is coupled to the first memory block. The second sense amplifier is coupled to the second memory block. The first circuit is coupled to the data bus and the first sense amplifier. The first circuit switches from precharging the data bus to providing data when the first memory block is selected and is decoupled from the data bus in response to the first memory block being deselected. The second circuit is coupled to the data bus and the second sense amplifier. The second circuit switches from precharging the data bus to providing data when the second memory block is selected and is decoupled from the data bus in response to the second memory block being deselected.

Abstract: A method for forming a semiconductor device includes providing a first integrated circuit having a landing pad and attaching a second integrated circuit to the first integrated circuit using at least one bonding layer. The second integrated circuit has an inter-circuit trace, the inter-circuit trace has an inter-circuit trace opening. The method further includes forming an opening through the second integrated circuit, the opening extending through the inter-circuit trace opening, forming a selective barrier on exposed portions of the inter-circuit trace in the opening, extending the opening through the at least one bonding layer to the landing pad, and filling the opening with a conductive fill material. The selective barrier layer comprises at least one of cobalt or nickel, and the conductive fill material electrically connects the inter-circuit trace and the landing pad.

Abstract: A contention-free keeper circuit including a keeper circuit having a first node and a second node, is provided. The contention-free keeper circuit may further include a delay element for providing time delay. The contention-free keeper circuit may further include a high-to-low contention element coupled between the first node and a first supply, and coupled to the delay element output. The contention-free keeper circuit may further include a low-to-high contention elimination element coupled between the first node and a second supply, and coupled to the delay element output, (i) wherein responsive to a low-to-high transition at the first node and the time delay, the low-to-high contention elimination element eliminates a low-to-high contention within the keeper circuit, and (ii) wherein responsive to a high-to-low signal transition at the first node and the time delay, the high-to-low contention elimination element eliminates a high-to-low contention within the keeper circuit.

Abstract: A memory circuit includes a sense amplifier in which a single reference signal is compared to two data signals from two memory cells. The reference signal is generated from the combination of memory cells in opposite logic states. The data signal capacitance is matched to the reference signal capacitance. With reduced but matched capacitance both high speed and high sensitivity can be achieved.

Abstract: An integrated circuit with a low voltage read/write operation is provided. The integrated circuit may include a processor and a plurality of memory cells organized in rows and columns and coupled to the processor, wherein a row of memory cells comprises a word line and all of the memory cells coupled to the word line, and wherein a column of memory cells comprises a bit line and all of the memory cells coupled to the bit line. The integrated circuit may further include a first power supply voltage terminal for receiving a first power supply voltage, wherein the first power supply voltage is provided to power the processor, and wherein the first power supply voltage is provided to power the plurality of memory cells during a first access operation of the plurality of memory cells.

Abstract: An analog to digital converter including a plurality of multiple independent gate field effect transistors (MIGFET) that provide a plurality of digital output signals, is provided. Each MIGFET of the plurality of MIGFETs may have first gate for receiving an analog signal, a second gate for being biased, and a current electrode for providing a digital output signal from among the plurality of the digital output signals. Each MIGFET of the plurality of MIGFETs may have a combination of body width, channel length that is unique among the plurality of MIGFETs to result in a threshold voltage that is unique among the plurality of MIGFETs. A digital to analog converter including a plurality of MIGFETs is also provided.