Abstract: A semiconductor memory device in which a storage electrode of a storage capacitor of a memory cell is formed by a selective chemical vapor deposition (CVD) technique. A lithography process is not required when forming the storage electrode. There is no narrowing of the storage electrode pattern and the minimum distance between adjacent storage electrodes can be made smaller than the minimum wiring dimension. The storage capacitance of the semiconductor memory device can be increased and a high storage capacitance is obtained.