Abstract: Circuitry, which is compatible with incandescent light dimmers, is disposed within the screwbase of a compact fluorescent light, and sets driving frequencies for a mercury plasma, based, at least in part, on sensing the duty cycle of the incoming AC supply waveform. In this way, existing lighting infrastructure, including phase-cut dimmer circuits for incandescent light bulbs, may be preserved, and incandescent bulbs can be replaced with compact fluorescent lights equipped with circuitry in accordance with the present invention. In a further aspect, the circuitry synchronizes the bulb drive signals with the AC power line frequency.

Abstract: Apparatus and methods are provided for wafer translators having a silicon core, an isolating conductive ground plane, and copper and subjacent resin layers disposed on the ground plane. A silicon substrate having at least one major surface coated with an electrically conductive layer is subjected to a number of printed circuit board manufacturing operations including, but not limited to, application of resin-coated copper foils; mechanical grinding of copper layers; mechanical drilling of via openings in a dielectric material; plating of copper, nickel, and gold layers; laser removal of metal; and chemical removal of metal; in order to produce a wafer translator having a silicon core. In further aspects of the present invention, alignment marks are formed and contact structures, such as stud bumps, are placed relative to a local set of alignment marks.

Abstract: Ion implantation is used to modify the chemical properties of portions of a material, such that the modified portions respond differently to a chemical etching operation than do the unmodified portions of the material. In a further aspect of the present invention, ion implants into a wafer are performed at different energies so as to form three-dimensional patterns of chemically modified material within the body of a wafer. In a still further aspect of the present invention, three-dimensional patterns of etched tunnels within a wafer are formed, and in some embodiments provide for reduced parasitic capacitance and/or reduced leakage currents for electronic circuits.

Abstract: Collecting process characterization data local to a failed integrated circuit (IC), includes providing a wafer having ICs, each IC having contact terminals, the wafer having process characterization test sites distributed across it such that at least one process characterization test site is adjacent each IC; selecting two or more ICs for simultaneous testing; for each of those ICs, coupling two or more contact terminals of the selected IC, and a corresponding two or more contact terminals of an associated test site to corresponding input terminals of a multiplexer, each multiplexer having an output terminal and a select control input terminal, the multiplexer operable to selectively provide an electrical pathway between either an IC contact terminal or a test site contact terminal and the multiplexer output terminal; coupling the output terminal of each multiplexer to a tester channel; operating the multiplexer so that its output terminal is coupled to the IC contact terminal; simultaneously testing two or m

Abstract: An apparatus for providing electrical pathways between one or more unsingulated integrated circuits and one or more test circuits external to the integrated circuits, includes a flexible substrate having a first major surface and a second major surface, a plurality of first contact structures disposed in a central portion of the first surface of the flexible substrate, a plurality of second contact structures disposed in a peripheral annular region of the first surface of the flexible substrate, and a plurality of first electrically conductive pathways, each of the plurality of first electrically conductive pathways coupled to a respective first and second contact structure, wherein the second surface is free from first contact structures, second contact structures, and first electrically conductive pathways.

Abstract: A translated wafer stand-in tester, being a hybrid apparatus capable of emulating the form factor and some or all behaviors of a translated wafer under test, which is operable to store, quantify, encode and convey, either directly or remotely, data from a testing system, including but not limited to pad pressure, electrical contact and temperature. The translated wafer stand-in tester may include several stacked and attached layers, at least one internal layer including electronic components operable to interact with a test system.

Abstract: Methods and apparatus for producing fully tested unsingulated integrated circuits without probe scrub damage to bond pads includes forming a wafer/wafer translator pair removably attached to each other wherein the wafer translator includes contact structures formed from a soft crushable electrically conductive material and these contact structures are brought into contact with the bond pads in the presence of an inert gas; and subsequently a vacuum is drawn between the wafer and the wafer translator. In one aspect of the present invention, the unsingulated integrated circuits are exercised by a plurality of test systems wherein the bond pads are never physically touched by the test system and electrical access to the wafer is only provided through the inquiry-side of the wafer translator. In a further aspect of the present invention, known good die having bond pads without probe scrub marks are provided for incorporation into products.

Abstract: Concurrent electrical access to the pads of integrated circuits on a wafer is provided by an edge-extended wafer translator that carries signals from one or more pads on one or more integrated circuits to contact terminals on the inquiry-side of the edge-extended wafer translator, including portions of the inquiry-side that are superjacent the wafer when the wafer and the edge-extended wafer translator are in a removably attached state, and portions of the inquiry side that reside outside a region defined by the intersection of the wafer and the edge-extended wafer translator. In a further aspect of the present invention, access to the pads of integrated circuits on a wafer is additionally provided by contact terminals in a second inquiry area located on the wafer-side of the edge-extended wafer translator in a region thereof bounded by its outer circumference and the circumference of the attached wafer.

Abstract: Assemblies include a substrate, such as a printed circuit board, with a first array of contact pads disposed thereon; a guide ring structure disposed on the substrate and at least partially surrounding the first array of contact pads; a translator socket disposed on the first array of contact pads, the translator socket adapted to receive the tester side of a translated wafer; a thermally conductive, conformal, heat spreading cushion adapted to be disposed over the backside of a wafer; a cover plate adapted to fit over the first array of contact pads, align with the guide ring structure, contain within it the various components disposed over the first array of contact pads, and removably attach to the substrate; and a bolster plate adapted to removably attach to a second side of the substrate.

Abstract: A voice-activated, or voice-operated, remote control is adapted to reduce or eliminate the sound output of one or more entertainment appliances in order quiet the environment and thereby improve the effectiveness and accuracy its voice recognition functions. In one aspect of the present invention, the remote control sends a mute command to an appliance under control and listens for a voice command during an ensuing predetermined time period. In a further aspect of the present invention, the remote control determines which one of a plurality of unmute sequences is to be transmitted.

Abstract: Memory modules address the growing gap between main memory performance and disk drive performance in computational apparatus such as personal computers. Memory modules disclosed herein fill the need for substantially higher storage capacity in end-user add-in memory modules. Such memory modules accelerate the availability of applications, and data for those applications. An exemplary application of such memory modules is as a high capacity consumer memory product that can be used in Hi-Definition video recorders. In various embodiments, memory modules include a volatile memory, a non-volatile memory, and a command interpreter that includes interfaces to the memories and to various busses. The first memory acts as an accelerating buffer for the second memory, and the second memory provides non-volatile backup for the first memory. In some embodiments data transfer from the first memory to the second memory may be interrupted to provide read access to the second memory.

Abstract: A conductor carrier provides, separately manufactured, conductive pathways, on a wafer level, which may be coupled to a wafer of fully fabricated integrated circuits. Such conductor carriers include an insulating body having two major surfaces with conductors disposed on each of those surfaces, and conductors disposed within the insulating body so as to provide signal continuity between various conductors on each of the two surfaces. An assembly can be formed by permanently or removably attaching the conductor carrier to the wafer. Conductor carriers may include an evacuation pathway suitable for removing air, or other gases, from between the conductor and the wafer so as to create a pressure differential that urges the conductor carrier into contact with the wafer. Conductor carriers may include a groove which is suitable for receiving a sealing ring; and may include a street map which is suitable for providing guidance to a wafer sawing operation.

Abstract: A metallization pattern for a wafer translator provides a high density layout of interdigitated contact pads, suitable for component placement, along with larger contact pads suitable for connection to external equipment terminals. In another aspect, electrically conductive material may be added to, or removed from, the high density layout of interdigitated contact pads and larger contact pads to modify, or reconfigure, the electrical pathways of the wafer translator.

Abstract: A flexible extension wafer translator includes a wafer translator portion, one or more flexible connectors extending outwardly therefrom, and a connector tab coupled to the distal end of each outwardly extending flexible connector. The flexible connectors may take any suitable form, including but not limited to, draped and pleated.

Abstract: A translated wafer stand-in tester (TWST), being a hybrid apparatus capable of emulating the form factor and some or all behaviors of a translated wafer under test, which is operable to store, quantify, encode and convey, either directly or remotely, data from a testing system, including but not limited to pad pressure, electrical contact and temperature. The TWST may include several stacked and attached layers, at least one internal layer including electronic components operable to interact with a test system.

Abstract: An apparatus, suitable for coupling a pads of integrated circuits on wafer to the pogo pins of a pogo tower in a test system without the need of a probe card, includes a body having a first surface and a second surface, the body having a substantially circular central portion, and a plurality of bendable arms extending outwardly from the central portion, each bendable arm having a connector tab disposed at the distal end thereof; a first plurality of contact terminals disposed on the second surface of the central portion of the body, the first plurality of contact terminals arranged in pattern to match the layout of pads on a wafer to be contacted; at least one contact terminal disposed on the first surface of the plurality of connector tabs; and a plurality of electrically conductive pathways disposed in the body such that each of the first plurality of contact terminals is electrically connected to a corresponding one of the contact terminals on the first surface of the connector tabs.

Abstract: A wafer/wafer translator pair in the attached state, with the wafer translator extending beyond the outer circumference of the wafer, is disposed on a rotation stage. At least one surface of the edge-extended wafer translator, in a peripheral annular region, provides contact pads electrically coupled to corresponding pads on the wafer, and a caliper-style contact block, operable to move perpendicularly the edge-extended wafer translator is positioned such the contact pads of the annular region may be electrically engaged with the contact block. After electrical communication between the wafer and the contact block, the contact block moves to a disengagement position, the rotation stage rotates the wafer/wafer translator pair to a new position and the contact block may then move into engagement with different contact pads in the annular region.

Abstract: An apparatus for providing electrical pathways between one or more unsingulated integrated circuits and one or more test circuits external to the integrated circuits, includes a flexible substrate having a first major surface and a second major surface, a plurality of first contact structures disposed in a central portion of the first surface of the flexible substrate, a plurality of second contact structures disposed in a peripheral annular region of the first surface of the flexible substrate, and a plurality of first electrically conductive pathways, each of the plurality of first electrically conductive pathways coupled to a respective first and second contact structure, wherein the second surface is free from first contact structures, second contact structures, and first electrically conductive pathways.

Abstract: A low-cost alignment system suitable for aligning a wafer to a test fixture includes a bundle of optical fibers wherein at least one fiber serves to deliver illumination to the alignment target from an end thereof, and a plurality of receiver fibers, each having ends with a known spatial relationship to the end of the illuminator fiber. The ends of the fiber bundle have a known spatial relationship to the fixture. In some embodiments, the fiber bundle is disposed within the fixture such that there is an unobscured optical path between the wafer and the receiving and illuminating ends of the fibers. In some embodiments, the fiber bundle is coupled to a light source and a light sensor mounted on the fixture. In some embodiments the alignment target is one or more bonding pads disposed on a wafer.

Abstract: Concurrent electrical access to the pads of integrated circuits on a wafer is provided by an edge-extended wafer translator that carries signals from one or more pads on one or more integrated circuits to contact terminals on the inquiry-side of the edge-extended wafer translator, including portions of the inquiry-side that are superjacent the wafer when the wafer and the edge-extended wafer translator are in a removably attached state, and portions of the inquiry side that reside outside a region defined by the intersection of the wafer and the edge-extended wafer translator. In a further aspect of the present invention, access to the pads of integrated circuits on a wafer is additionally provided by contact terminals in a second inquiry area located on the wafer-side of the edge-extended wafer translator in a region thereof bounded by its outer circumference and the circumference of the attached wafer.