Abstract: A system and method for identifying which incoming write data is valid and for insuring that stale data does not overwrite valid data within system memory within a symmetrical multiprocessor data processing system. Upon receipt of a Load Miss request from a processor, a stale bit is established and set equal to zero. A determination is then made of which other processor has ownership of the requested cache line. The requested cache line is then transferred in a cache-to-cache transfer from the second processor to the first processor. If the first processor further modifies the cache line and writes back the cache line to system memory before the original owner of the cache line writes back the stale data with an acknowledgment of the cache-to-cache transfer, the stale bit is set to one. Upon receipt from the acknowledgment from the original owner of the cache line, the stale data is dropped when it is determined that the stale bit has been set.

Abstract: A system and method whereby the cursor displayed by a data processing system on a monitor is automatically moved to a preselected location on the desktop, called the parking area, whenever it has been inactive for a predetermined amount of time. If the window focus is dependent on the location of the cursor, the parking area can be located within a specified window.

Abstract: An information handling system includes one or more processors, a system bus or network connecting the processors, a memory system connected to the system bus, an asynchronous signal controller connected to the system bus, one or more I/O bridges connected to the system bus, an I/O bus connected to each I/O bridge, one or more devices connected to the I/O bus, including perhaps another I/O-bus-to-I/O-bus bridge where additional devices may be connected to a second I/O bus, wherein the first or host bridge includes remote interrupt control logic having a register wherein an input to each position in the register is from one of the I/O devices downstream from the host bridge, and a shadow register address buffer, both under the control of a sample circuit connected to outputs of the register such that when a change in any register position is detected by the sample circuit, the entire contents of the register are sent to the shadow register indicated in the shadow register address buffer by a processor bypass t

Abstract: An apparatus (10,110,210) for facilitating the removal of a condom (12,112,212) from a penis (14,114,214) and for preventing the entanglement of the condom (12,112,212) with pubic hair (16,116,216) located on the penis (14,114,214) and on the pubic area (18,118,218) adjacent the penis (14,114,214). The apparatus (10,110,210) comprises an elongated tubular sleeve (24,124,224) having a first open end (26,126,226), a second open end (28,128,228) and a flange (20,120,220) extending radially outwardly from the first open end (26,126,226).