Abstract: The present invention provides an output buffer having a self back-bias compensating circuit that adapts the effective output transistor size to overcome current-reducing threshold voltage shifts caused by connection of the output n-wells to a high voltage. More particularly, this invention provides a circuit configuration in which bias level detection is used to switch in additional PFET legs under high back bias conditions. The extra driver legs are disabled under zero back bias. This compensates for the effect that different voltage switching environments have on PFET performance.

Abstract: A program that can be launched during a browsing session logs protocol calls and stores time-stamped copies of those calls to a call list file. Calls that result in errors returned from the remote server or proxy are flagged, and may optionally be retained, or automatically or manually deleted. The program also creates a map file so as to keep information needed to associate a protocol call to the file or files downloaded in response to the protocol call. Filtering and tagging of downloaded files can optionally be performed to assist in the manual or automatic determination of whether to include the downloaded file(s) in a session file. Entries in the session file may be annotated with text, audio, video or various combinations of these and other media. The session file can be communicated to one or more users remote temporally, geographically, or both. The session file provides protocol calls to a user's local browser thus replaying the recorded browsing session as edited or annotated.

Abstract: The present invention provides a latching mechanism for use in high-speed domino logic pipestages. The latching mechanism allows time borrowing across latch boundaries, provides sufficient hold time for the output to be sensed by the next stage, and provides a circuit configuration in which race conditions related to the latching mechanism have inherent positive margin. The latching mechanism of the present invention is applicable to fully self-resetting domino logic, globally resetting domino logic, or any combination thereof. The latching mechanism is a set dominant latch having its set input driven by the output of the last domino logic gate in a pipestage, and having its reset input driven by the output of the last domino logic gate in a pipestage ANDed with a delayed version of the pulsed clock that triggers the domino chain of the pipestage.