Patents Represented by Attorney, Agent or Law Firm Reed Simth LLP
  • Patent number: 6821867
    Abstract: The present invention provides a semiconductor device and a manufacturing method thereof which can realize fine processing while preventing a warp of a semiconductor wafer. In forming a plurality of semiconductor elements on a semiconductor wafer, grooves for attenuating stress are formed in scribe regions defined between semiconductor element forming regions. Here, the grooves are formed in the scribe regions except for alignment pattern forming regions such that the alignment pattern forming regions remain in the scribe regions. On the alignment pattern forming regions of the scribe regions, an alignment pattern or a TEG pattern which is used in a photolithography step is formed.
    Type: Grant
    Filed: April 24, 2003
    Date of Patent: November 23, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Nobuyoshi Matsuura, Yasuhiko Kouno, Hideo Miura, Masaharu Kubo