Patents Represented by Attorney, Agent or Law Firm Reed Smith Crosby Heafey
  • Patent number: 6766315
    Abstract: A method and apparatus for intelligent Internet searching, the apparatus residing as a software application on a user's computer (the client). A single subject database of sources of directly and indirectly accessible content is stored on the client and accessed by the application. The database also necessary information for searching each source. Preferably, the database is updated at a regular interval. Multiple simultaneous hidden database searches may be performed by the application by linking the client to the appropriate database access pages on the network and forwarding the user's desired search information. Preferably, search results are updated and compared to highlight new information.
    Type: Grant
    Filed: November 1, 2000
    Date of Patent: July 20, 2004
    Inventors: Timothy G. Bratsos, Peter J. R. Bonney, Lynn W. Barr
  • Patent number: 6728945
    Abstract: A method and system are provided for computing behavioral level observabilities of a digital system. In one example, a logic network is provided for performing an observability analysis at the behavioral level of a digital system. The logic network includes logic objects configured to emulate behavioral observabilities computed from a control data flow graph (CDFG), wherein the logic objects include at least one of: first logic objects configured to compute a token observable condition (TOC) of an edge of the CDFG; and second logic objects configured to compute a node observable condition (NOC) of a node of the CDFG. A logic optimization is used to optimize the logic network to obtain an optimized logic network of the behavioral observabilities.
    Type: Grant
    Filed: February 26, 2001
    Date of Patent: April 27, 2004
    Assignee: Cadence Design Systems, Inc.
    Inventor: Qi Wang
  • Patent number: 6698002
    Abstract: A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk, upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, as a system on a chip, in compliance with the criteria and modified constraints, and substantially without changing the selected circuit block and the processing method.
    Type: Grant
    Filed: March 23, 2001
    Date of Patent: February 24, 2004
    Assignee: Cadence Design Systems, Inc.
    Inventors: Henry Chang, Larry Cooke, Merrill Hunt, Wuudiann Ke, Christopher K. Lennard, Grant Martin, Peter Paterson, Khoan Truong, Kumar Venkatramani
  • Patent number: 6691824
    Abstract: An improved strap for the construction of safety harnesses of the type designed to protect against falls provides increased flexibility and comfort. The strap is composed of a tubular sheath of elastic fabric that coaxially surrounds a typical high strength safety strap. The two components of the strap are sized so that the safety strap is longer than the surrounding tubular elastic sheath. This causes the longitudinal compression and thickening of the safety strap which then acts as filler to form a “pillow” from the sheath. This cushions the strap making it more comfortable while the longitudinal compression of the enclosed safety strap increases its flexibility. During a fall the sheath rapidly stretches and the enclosed safety strap elongates to full length to stop the fall in the normal manner of safety straps.
    Type: Grant
    Filed: October 12, 2001
    Date of Patent: February 17, 2004
    Assignee: Ultra-Safe, Inc.
    Inventor: C. Marty Sharp
  • Patent number: 6694501
    Abstract: A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk, upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, as a system on a chip, in compliance with the criteria and modified constraints, and substantially without changing the selected circuit block and the processing method.
    Type: Grant
    Filed: January 4, 2001
    Date of Patent: February 17, 2004
    Assignee: Cadence Design Systems, Inc.
    Inventors: Henry Chang, Larry Cooke, Merrill Hunt, Wuudiann Ke, Christopher K. Lennard, Grant Martin, Peter Paterson, Khoan Truong, Kumar Venkatramani
  • Patent number: 6693896
    Abstract: If an instruction is provided so as to receive second content information in place of first content information on the basis of only one operation by a user while the first content information is received through a connection formed in a communication network, the connection for communication of the first content information is disconnected, and thereafter, a connection for communication of the second content information is formed. In this manner, network resources can be reserved or released without consciousness of users.
    Type: Grant
    Filed: April 7, 2000
    Date of Patent: February 17, 2004
    Assignee: Sony Corporation
    Inventors: Shusuke Utsumi, Ryusuke Sawatari
  • Patent number: 6693665
    Abstract: A photographic apparatus is described which outputs a photographed image immediately to paper by a simple operation. The photographic apparatus includes an electronic camera for electronically acquiring an image, a connection base for removably connecting the electronic camera thereto, the connection base having a function of reading out image data from the electronic camera while the camera is connected thereto, and a printing section for acquiring the image data from the connection base and outputting an image based on the image data to paper.
    Type: Grant
    Filed: July 14, 1999
    Date of Patent: February 17, 2004
    Assignee: Sony Corporation
    Inventors: Mitsuyoshi Shindo, Hideki Wanami, Hikaru Kobayashi, Kiyotaka Dochi
  • Patent number: 6684208
    Abstract: A system and method for estimating the point of diminishing returns for additional information in data mining processing applications. The present invention provides a convenient method of estimating the extent to which a data mining algorithm captures useful information in raw feature data. First, the input data is processed using a forward transform. A region of overlap Yo in the forward transformed data is identified and quantified. The region of overlap Yo is processed with a reverse transform to create an overlap region Z in an original feature space. The degree of overlap in region Z is quantified and compared to a level of overlap in the Yo region, such that the comparison quantifies the extent to which a data mining algorithm captures useful information in the input data.
    Type: Grant
    Filed: May 15, 2001
    Date of Patent: January 27, 2004
    Assignee: Rockwell Technologies, LLC
    Inventors: David Kil, Ken Fertig
  • Patent number: 6678648
    Abstract: In an MPEG audio encoder, a sign and an absolute value calculation are performed outside of the quantization inner loop, thereby reducing redundant calculations. The stored sign and absolute values can also be used in the frame packing block, also increasing processing efficiency. Thus, the present invention improves the performance of an MPEG audio encoder.
    Type: Grant
    Filed: June 14, 2000
    Date of Patent: January 13, 2004
    Assignee: Intervideo, Inc.
    Inventor: Fahri Surucu
  • Patent number: 6672714
    Abstract: Of the first sheet formed of piezoelectric materials and the second sheet formed of prescribed materials, the upper electrode layer formed of conduction materials is formed on one surface of the first sheet and the lower electrode layer formed of conduction materials is formed on the other surface of said first sheet or on one surface of the second sheet. And the first and the second sheets are piled and densified having the lower electrode layer between, and a piezoelectric actuator will be manufactured by patterning the upper electrode layer or the lower electrode layer in order to form multiple electrodes corresponding respectively to each pressure chamber of the pressure chamber forming unit.
    Type: Grant
    Filed: January 28, 2002
    Date of Patent: January 6, 2004
    Assignee: Sony Corporation
    Inventors: Toru Tanikawa, Hiroshi Tokunaga, Shota Nishi
  • Patent number: 6666682
    Abstract: An improved dental mirror for facilitating the accurate visualization and measurement of structures and distances and for facilitating the assessment of parallelism between non-adjacent teeth. The dental mirror includes an elongated handle having a longitudinal axis and affixed to one end thereof is a mirror frame. The mirror frame supports a planar mirror of rectangular geometry having a perimeter defined by a pair of major parallel edges and minor edges. A series of calibrations are provided along the perimeter of the mirror whereby at least one of the edges is calibrated by lines of demarcation. A plurality of angulations between handle axis and major parallel edge, in the plane of the mirror, is achievable by a rotation mechanism or on a series of fixed angle dental mirrors with different orientations.
    Type: Grant
    Filed: November 20, 2001
    Date of Patent: December 23, 2003
    Inventor: Peter G. Meyerhof
  • Patent number: 6666836
    Abstract: An improved device for attaching thermal dressings—using essentially any type of source of heat or cold employs a novel adhesive that permits firm attachment of the dressing to essentially any portion of the human anatomy with no need for wrapping around the limb or other anatomical region. The adhesive is sufficiently weak that the dressing can be peeled from the skin—even in the presence of body hair—with no pain. The adhesive, a hypoallergenic hydrophilic gel, is thick and soft and adheres by molding itself to the skin surface, and into and around hair shafts. The material contains essentially no elastomers and does not grip hair or pull strongly on hairs when the dressing is removed. When the gel becomes dehydrated, it loses most, if not all, of its adhesive properties. The gel is sufficiently crosslinked so as to resist dissolution by additional water.
    Type: Grant
    Filed: April 6, 2001
    Date of Patent: December 23, 2003
    Assignee: STI Medical Products, Inc.
    Inventor: Steve T. Islava
  • Patent number: 6654994
    Abstract: The present invention relates to hoisting and handling systems and methods. The present invention is a system and method to facilitate the hoisting, positioning, installation and removal of continuous track drive units. Continuous track drive units are used as a means for propelling certain vehicles, such as farm tractors, construction machines and military vehicles. The present invention allows for simplified, efficient handling and transfer of continuous track drive units.
    Type: Grant
    Filed: March 16, 2001
    Date of Patent: December 2, 2003
    Inventor: Mark LaFevers
  • Patent number: 6631470
    Abstract: A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk, upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, as a system on a chip, in compliance with the criteria and modified constraints, and substantially without changing the selected circuit block and the processing method.
    Type: Grant
    Filed: March 23, 2001
    Date of Patent: October 7, 2003
    Assignee: Cadence Design Systems, Inc.
    Inventors: Henry Chang, Larry Cooke, Merrill Hunt, Wuudiann Ke, Christopher K. Lennard, Grant Martin, Peter Paterson, Khoan Truong, Kumar Venkatramani
  • Patent number: 6629293
    Abstract: A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk, upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, as a system on a chip, in compliance with the criteria and modified constraints, and substantially without changing the selected circuit block and the processing method.
    Type: Grant
    Filed: February 23, 2001
    Date of Patent: September 30, 2003
    Assignee: Cadence Design Systems, Inc.
    Inventors: Henry Chang, Larry Cooke, Merrill Hunt, Wuudiann Ke, Christopher K. Lennard, Grant Martin, Peter Paterson, Khoan Truong, Kumar Venkatramani
  • Patent number: 6620018
    Abstract: A simulated jet fan is mounted inside a flying toy to provide propulsion. A tether attached to a mounting plate and the flying toy directs the flying toy in a circular motion. In one embodiment, the simulated jet fan is an impeller enclosed in a housing. The impeller is attached to an electric motor powered by batteries. The flying toy includes air inlets coupled to an air intake of the fan, and exhaust ports direct air expelled from the fan toward a rear of the flying toy, providing propulsion. Wings may be attached to the toy to assist in “flying.” The attached wings may be fixed or moveable. In one embodiment, flapping wings powered by an electric motor are attached giving the flying toy additional propulsion and a pleasing nature.
    Type: Grant
    Filed: April 19, 2001
    Date of Patent: September 16, 2003
    Inventors: Justin Chao, Joseph Tean
  • Patent number: 6622290
    Abstract: A method for timing verification of very large scale integrated circuits reduces required CPU speed and memory usage. The method involves steps including partitioning the circuit into a plurality of blocks and then partitioning the verification between shell path components and core path components. Timing verification is then conducted for only shell path components while core path components are abstracted or ignored. Finally, timing verification for core path components in each block completes the process for the entire design.
    Type: Grant
    Filed: October 3, 2000
    Date of Patent: September 16, 2003
    Assignee: Cadence Design Systems, Inc.
    Inventors: Arnold Ginetti, Mark Steven Hahn, Harish Kriplani, Naser Awad
  • Patent number: 6622291
    Abstract: A feasible floorplan of a circuit is determined and budgeted in the early phases of circuit design. The process of determining the floorplan and budget includes estimating RTL complexity, physical partitioning, block placement, block i/o placement and top level global routing, and verifying feasibility of the floorplan. Allocation of global timing constraints to each block is performed by producing logic cones representing timing of circuit paths in each block. The circuit paths are optimized to determine a feasible timing for each block. The global constraints are allocated proportionally to each block based on the feasible timing for each block.
    Type: Grant
    Filed: October 30, 2000
    Date of Patent: September 16, 2003
    Assignee: Cadence Design Systems, Inc.
    Inventor: Arnold Ginetti
  • Patent number: D479647
    Type: Grant
    Filed: July 26, 2002
    Date of Patent: September 16, 2003
    Assignee: Mama's of Invention, Inc.
    Inventors: Angela Paura, Teri Seide, Catherine A. Paura
  • Patent number: D485198
    Type: Grant
    Filed: October 1, 2002
    Date of Patent: January 13, 2004
    Assignee: STI Medical Products
    Inventor: Steven T Islava