Patents Represented by Attorney, Agent or Law Firm Reed Smith Crosby Heafey LLP
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Patent number: 6766315Abstract: A method and apparatus for intelligent Internet searching, the apparatus residing as a software application on a user's computer (the client). A single subject database of sources of directly and indirectly accessible content is stored on the client and accessed by the application. The database also necessary information for searching each source. Preferably, the database is updated at a regular interval. Multiple simultaneous hidden database searches may be performed by the application by linking the client to the appropriate database access pages on the network and forwarding the user's desired search information. Preferably, search results are updated and compared to highlight new information.Type: GrantFiled: November 1, 2000Date of Patent: July 20, 2004Inventors: Timothy G. Bratsos, Peter J. R. Bonney, Lynn W. Barr
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Patent number: 6728945Abstract: A method and system are provided for computing behavioral level observabilities of a digital system. In one example, a logic network is provided for performing an observability analysis at the behavioral level of a digital system. The logic network includes logic objects configured to emulate behavioral observabilities computed from a control data flow graph (CDFG), wherein the logic objects include at least one of: first logic objects configured to compute a token observable condition (TOC) of an edge of the CDFG; and second logic objects configured to compute a node observable condition (NOC) of a node of the CDFG. A logic optimization is used to optimize the logic network to obtain an optimized logic network of the behavioral observabilities.Type: GrantFiled: February 26, 2001Date of Patent: April 27, 2004Assignee: Cadence Design Systems, Inc.Inventor: Qi Wang
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Patent number: 6698002Abstract: A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk, upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, as a system on a chip, in compliance with the criteria and modified constraints, and substantially without changing the selected circuit block and the processing method.Type: GrantFiled: March 23, 2001Date of Patent: February 24, 2004Assignee: Cadence Design Systems, Inc.Inventors: Henry Chang, Larry Cooke, Merrill Hunt, Wuudiann Ke, Christopher K. Lennard, Grant Martin, Peter Paterson, Khoan Truong, Kumar Venkatramani
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Patent number: 6694501Abstract: A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk, upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, as a system on a chip, in compliance with the criteria and modified constraints, and substantially without changing the selected circuit block and the processing method.Type: GrantFiled: January 4, 2001Date of Patent: February 17, 2004Assignee: Cadence Design Systems, Inc.Inventors: Henry Chang, Larry Cooke, Merrill Hunt, Wuudiann Ke, Christopher K. Lennard, Grant Martin, Peter Paterson, Khoan Truong, Kumar Venkatramani
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Patent number: 6693665Abstract: A photographic apparatus is described which outputs a photographed image immediately to paper by a simple operation. The photographic apparatus includes an electronic camera for electronically acquiring an image, a connection base for removably connecting the electronic camera thereto, the connection base having a function of reading out image data from the electronic camera while the camera is connected thereto, and a printing section for acquiring the image data from the connection base and outputting an image based on the image data to paper.Type: GrantFiled: July 14, 1999Date of Patent: February 17, 2004Assignee: Sony CorporationInventors: Mitsuyoshi Shindo, Hideki Wanami, Hikaru Kobayashi, Kiyotaka Dochi
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Patent number: 6684208Abstract: A system and method for estimating the point of diminishing returns for additional information in data mining processing applications. The present invention provides a convenient method of estimating the extent to which a data mining algorithm captures useful information in raw feature data. First, the input data is processed using a forward transform. A region of overlap Yo in the forward transformed data is identified and quantified. The region of overlap Yo is processed with a reverse transform to create an overlap region Z in an original feature space. The degree of overlap in region Z is quantified and compared to a level of overlap in the Yo region, such that the comparison quantifies the extent to which a data mining algorithm captures useful information in the input data.Type: GrantFiled: May 15, 2001Date of Patent: January 27, 2004Assignee: Rockwell Technologies, LLCInventors: David Kil, Ken Fertig
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Patent number: 6666682Abstract: An improved dental mirror for facilitating the accurate visualization and measurement of structures and distances and for facilitating the assessment of parallelism between non-adjacent teeth. The dental mirror includes an elongated handle having a longitudinal axis and affixed to one end thereof is a mirror frame. The mirror frame supports a planar mirror of rectangular geometry having a perimeter defined by a pair of major parallel edges and minor edges. A series of calibrations are provided along the perimeter of the mirror whereby at least one of the edges is calibrated by lines of demarcation. A plurality of angulations between handle axis and major parallel edge, in the plane of the mirror, is achievable by a rotation mechanism or on a series of fixed angle dental mirrors with different orientations.Type: GrantFiled: November 20, 2001Date of Patent: December 23, 2003Inventor: Peter G. Meyerhof
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Patent number: 6631470Abstract: A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk, upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, as a system on a chip, in compliance with the criteria and modified constraints, and substantially without changing the selected circuit block and the processing method.Type: GrantFiled: March 23, 2001Date of Patent: October 7, 2003Assignee: Cadence Design Systems, Inc.Inventors: Henry Chang, Larry Cooke, Merrill Hunt, Wuudiann Ke, Christopher K. Lennard, Grant Martin, Peter Paterson, Khoan Truong, Kumar Venkatramani
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Patent number: 6629293Abstract: A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk, upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, as a system on a chip, in compliance with the criteria and modified constraints, and substantially without changing the selected circuit block and the processing method.Type: GrantFiled: February 23, 2001Date of Patent: September 30, 2003Assignee: Cadence Design Systems, Inc.Inventors: Henry Chang, Larry Cooke, Merrill Hunt, Wuudiann Ke, Christopher K. Lennard, Grant Martin, Peter Paterson, Khoan Truong, Kumar Venkatramani
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Patent number: 6620018Abstract: A simulated jet fan is mounted inside a flying toy to provide propulsion. A tether attached to a mounting plate and the flying toy directs the flying toy in a circular motion. In one embodiment, the simulated jet fan is an impeller enclosed in a housing. The impeller is attached to an electric motor powered by batteries. The flying toy includes air inlets coupled to an air intake of the fan, and exhaust ports direct air expelled from the fan toward a rear of the flying toy, providing propulsion. Wings may be attached to the toy to assist in “flying.” The attached wings may be fixed or moveable. In one embodiment, flapping wings powered by an electric motor are attached giving the flying toy additional propulsion and a pleasing nature.Type: GrantFiled: April 19, 2001Date of Patent: September 16, 2003Inventors: Justin Chao, Joseph Tean
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Patent number: 6622291Abstract: A feasible floorplan of a circuit is determined and budgeted in the early phases of circuit design. The process of determining the floorplan and budget includes estimating RTL complexity, physical partitioning, block placement, block i/o placement and top level global routing, and verifying feasibility of the floorplan. Allocation of global timing constraints to each block is performed by producing logic cones representing timing of circuit paths in each block. The circuit paths are optimized to determine a feasible timing for each block. The global constraints are allocated proportionally to each block based on the feasible timing for each block.Type: GrantFiled: October 30, 2000Date of Patent: September 16, 2003Assignee: Cadence Design Systems, Inc.Inventor: Arnold Ginetti
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Patent number: 6622290Abstract: A method for timing verification of very large scale integrated circuits reduces required CPU speed and memory usage. The method involves steps including partitioning the circuit into a plurality of blocks and then partitioning the verification between shell path components and core path components. Timing verification is then conducted for only shell path components while core path components are abstracted or ignored. Finally, timing verification for core path components in each block completes the process for the entire design.Type: GrantFiled: October 3, 2000Date of Patent: September 16, 2003Assignee: Cadence Design Systems, Inc.Inventors: Arnold Ginetti, Mark Steven Hahn, Harish Kriplani, Naser Awad
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Patent number: 6607384Abstract: Disclosed is a lighting device for use with a dental or medical instrument having a tool in the distal part of the instrument for treatment of a site. The lighting device includes a plurality of LEDs and an LED holder encasing the plurality of LEDs and capable of being mounted on a distal part of the instrument. The LEDs are arranged so as to illuminate the site substantially without casting a shadow on the site in treatment when the LED holder is mounted on the instrument. Also disclosed is a dental or medical instrument including a tool in the distal part of the instrument for treatment of a site and a lighting device. The lighting device further includes a plurality of LEDs and an LED holder encasing the LEDs and provided in the distal part of the instrument. The LEDs are arranged so as to illuminate the site substantially without casting a shadow on the site in treatment.Type: GrantFiled: October 19, 2000Date of Patent: August 19, 2003Assignee: Nakanishi Inc.Inventor: Kensuke Nakanishi
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Patent number: 6606127Abstract: A method and apparatus for synchronizing multiple signals is provided. The method and apparatus utilize the timing information of one of the multiple signals as a reference clock for synchronizing multiple signals. The method and apparatus utilize selectively gating the clocks of the other signal processing chains in order to allow control by the reference clock.Type: GrantFiled: June 9, 2000Date of Patent: August 12, 2003Assignee: Enseo, Inc.Inventors: William C. Fang, Raymond S. Horton
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Patent number: 6603285Abstract: A power circuit is provided so that a charge can be normally driven even during replacement of a first battery. This power circuit comprises: first and second batteries for driving a charge; a first battery voltage detection means; a first switch for controlling a second battery power supply path based on an output of the voltage detection means; an overcharge prevention means for preventing an overcharge for the secondary battery caused by the first battery; and a switch controlled by an output of the overcharge prevention means.Type: GrantFiled: September 18, 2001Date of Patent: August 5, 2003Assignee: Sony CorporationInventors: Koji Aoyagi, Kuniharu Onozuka
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Patent number: 6595904Abstract: An exercise apparatus providing resistance for hip and knee strengthening without increasing joint loading or shear force beyond that imparted by muscle contraction. A preferred embodiment includes a portable embodiment to allow continued use throughout changes in exercise environment.Type: GrantFiled: November 18, 2000Date of Patent: July 22, 2003Inventor: Daniel Louis Staffa
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Patent number: 6593308Abstract: The invention is a drug delivery system of a delivery vehicle having a low molecular weight hyaluronan ligand with an affinity for CD44 receptors. Preferably, the delivery vehicle is a liposome but other suitable delivery vehicles include microspheres, micelles, emulsions, lipid discs, polymers, viral particles and viruses. The systems of the invention may further comprise a drug, which can be any anticancer agent or other therapeutic or diagnostic agent. The invention also comprises methods of delivering a drug to a cell that expresses CD44 by contacting the cell with the drug delivery system. Further methods include treating a patient with cancer and targeting drug delivery to cells that express CD44 by attaching a glycosaminoglycan ligand.Type: GrantFiled: December 3, 1999Date of Patent: July 15, 2003Assignee: The Regents of the University of CaliforniaInventor: Francis C. Szoka, Jr.
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Patent number: 6590373Abstract: A regenerative load apparatus and a load test method are able to reduce a test cost required when a load testis effected on apparatus for supplying electric power to a load. The regenerative load apparatus includes a first load (22) for transmitting supplied electric power at a current conversion ratio approximately inverse relative to that of a tested apparatus (21) from an output side, a second load (23) for consuming supplied electric power and a power supply (24) for supplying electric power approximately equal to electric power consumed by the second load (23) to the tested apparatus (21), wherein electric power is diverged and supplied to the first load (22) and the second load (23) from the tested apparatus (21) and the electric power transmitted from the first load (22) is supplied to the tested apparatus (21) in addition to the electric power from the power supply 24.Type: GrantFiled: June 17, 2002Date of Patent: July 8, 2003Assignee: Sony CorporationInventor: Tamihei Hiramatsu
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Patent number: 6561801Abstract: There is disclosed a light guide unit including a bunch of glass fibers capable of transmitting light from a light source to a desired site, a sheath of a thermocontracting resin contracted to cover the bunch of glass fibers for substantially its overall length, and a filler of a hardening resin hardened to fill spaces between the glass fibers within the sheath. Also disclosed are a method for producing the light guide unit, and a dental handpiece having the light guide unit.Type: GrantFiled: May 2, 2000Date of Patent: May 13, 2003Assignee: Nakanishi Inc.Inventor: Takasuke Nakanishi
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Patent number: 6552822Abstract: A multiple-level error diffusion processing is performed to obtain an image of a high quality with uniform texture and reduced roughness, while reducing a gradation level. An image processing apparatus comprises a first error diffusion processing section for selectively performing error diffusion processing on input image data according to its gradation values and a second error diffusion processing section for performing error diffusion processing of three or more quantization levels on the output data of the first error diffusion processing section for outputting as output image data. A selective quantization section of the first error diffusion processing section performs such a quantization that errors are supplemented selectively centering a portion where no error is produced through quantization in a quantization section of the second error diffusion processing section.Type: GrantFiled: February 23, 1999Date of Patent: April 22, 2003Assignee: Sony CorporationInventor: Masaki Kishimoto