Abstract: A circuit for regulating the gain of a variable differential gain amplifier. In one embodiment, a fully differential amplifier amplifies the outputs of the variable gain amplifier. The outputs of the fully differential amplifier are applied to a three input comparator so that if either of the outputs are greater than a reference voltage, a control signal is generated which is used to regulate the gain of the variable gain amplifier. In other embodiments, an analog OR function is used as an input to a conventional two input comparator in place of the three input comparator. In another embodiment, outputs of the variable gain amplifier are passed through switches to a scaling circuit which either voltage divides or amplifies and combines the outputs before application to a comparator. In each case, known asymmetries can be compensated for by independent gain control of each of the outputs of the variable gain differential amplifier.

Abstract: A test mode structure and method of a multi-power-source device provides for the device to remain in a test mode, during which current draw of the device may be accurately measured, even after primary power supply to the device has been greatly reduced or completely removed. Significant reduction or removal of the primary power supply while still remaining in the test mode is necessary to counter the presence of a variable current that would otherwise be normally generated by the multi-power-source device in the test mode; the presence of the variable current during the test mode, if not negated, will not permit an accurate measurement of the current draw of the multi-power-source device. Significant reduction or removal of the primary power supply to the device would typically cause the multi-power-source device to exit the test mode and switch to a secondary supply voltage supplied by the secondary power supply, thereby foiling any attempt to measure the current draw of the device.

Abstract: Programmability of the data background patterns used to test random-access-memories (RAMs) is accomplished by adding to the memory input/output (I/O) buffers of RAM memory, for each data bit of a data background pattern to be programmed, a programming mechanism and a selection mechanism. The programming mechanism is capable of programming a data bit of the data background pattern in accordance with a programming information signal provided to the RAM. The selection mechanism provides either the programmed data bit or a normal, application data bit to an input/output buffer of the RAM in accordance with whether the RAM is in a test mode or a normal operating mode, as indicated by a test control signal provided to the RAM.

Abstract: A test mode structure and method of a multi-power-source device provides for the device to remain in a test mode, during which current draw of the device may be accurately measured, even after primary power supply to the device has been greatly reduced or completely removed. Significant reduction or removal of the primary power supply while still remaining in the test mode is necessary to counter the presence of a variable current that would otherwise be normally generated by the multi-power-source device in the test mode; the presence of the variable current during the test mode, if not negated, will not permit an accurate measurement of the current draw of the multi-power-source device. Significant reduction or removal of the primary power supply to the device would typically cause the multi-power-source device to exit the test mode and switch to a secondary supply voltage supplied by the secondary power supply, thereby foiling any attempt to measure the current draw of the device.

Abstract: A circuit for regulating the gain of a variable differential gain amplifier. In one embodiment, a fully differential amplifier amplifies the outputs of the variable gain amplifier. The outputs of the fully differential amplifier are applied to a three input comparator so that if either of the outputs are greater than a reference voltage, a control signal is generated which is used to regulate the gain of the variable gain amplifier. In other embodiments, an analog OR function is used as an input to a conventional two input comparator in place of the three input comparator. In another embodiment, outputs of the variable gain amplifier are passed through switches to a scaling circuit which either voltage divides or amplifies and combines the outputs before application to a comparator. In each case, known asymmetries can be compensated for by independent gain control of each of the outputs of the variable gain differential amplifier.

Abstract: An integrated circuit structure and method is capable of automatically tuning the duty cycle of a generated clock signal to any desired value. Tuning of the duty cycle depends upon the precise layout specifications of multiple delay elements of one or more multiplexing circuits of the integrated circuit device. Connecting one or more multiplexing circuits in a serial fashion allows a base frequency to be multiplied in order to produce a generated clock frequency of a desired frequency. Control of select lines to the multiplexing circuits allows the delay path through the one or more multiplexing circuits to be adjusted, thereby automatically adjusting the duty cycle of the generated clock signal.

Abstract: A power MOSFET suitable for use in RF applications and a method for making the same is disclosed. The power MOSFET has an increased distance between gate and drain regions of the device in order to decrease the device gate to drain capacitance Cgd. The distance between the gate and drain regions is increased by selective doping of a polysilicon layer of the gate to produce at least two polysilicon gate regions separated by a region of undoped polysilicon that is positioned over a substantial portion of the drain region that resides between the channel portions of the body region of the device. The addition of a contact oxide layer formed directly above the region of undoped polysilicon further increases the distance between gate and drain. Finally, a metal layer is deposited over the entire structure to form the gate and source electrodes of the device.

Abstract: A power supply switching circuit employs hysteresis to ensure stable, timely, and accurate transition between a primary power source and a secondary power source of an integrated circuit. A comparison element of the circuit compares a first voltage signal derived from a primary voltage of the primary power source to a second voltage signal provided by the secondary power source in order to generate a compare output signal. A voltage divider element of the circuit, characterized as having a RC constant, is coupled to the primary power source and receives the compare signal generated by the comparison element and generates the first voltage signal. A bypass element of the circuit is coupled to the voltage divider element and is controlled by the compare signal to bypass the RC constant of the voltage divider element by immediately pulling the first voltage signal to the primary voltage when, after powering up the primary power source, the first voltage signal becomes greater than the second voltage signal.

Abstract: A battery backed-up semiconductor device employs a Vss switching configuration to provide uninterrupted battery power to critical circuitry of the device even in the event of external conditions, such as undershoot, that threaten to corrupt data stored by the device. Both primary power and battery power, when needed, are supplied to floating wells of the device rather than to the device substrate, making the device immune to undershoots that can short the battery to the device substrate and corrupt data stored by the device. The device substrate is permanently tied to the positive power supply voltage and the positive terminal of the battery voltage and is therefore not subject to the concerns associated with switching from a failed primary power supply to the back-up battery power supply.

Abstract: A method and integrated circuit for providing drive signals to a polyphase dc motor. The integrated circuit is fabricated on a semiconductor substrate for providing drive signals to a polyphase dc motor. The circuit includes a coil drive circuit for connection to drive coils of the motor to selectively supply drive currents thereto in a predetermined sequence. A sequencer circuit commutatively selects the drive coils to which the drive currents are selectively supplied, and a motor, speed controlling circuit controls the speed of the motor by controlling the speed of commutation. A temperature sensing element, such as a diode, is fabricated in the substrate to indicate the temperature of the substrate, and a temperature measuring circuit is connected to the temperature sensing element and to the motor speed controlling circuit to operate the motor speed controlling circuit to slow the speed of the motor when the temperature of the substrate exceeds a first predetermined temperature.

Abstract: A power MOSFET suitable for use in RF applications and a method for making the same is disclosed. The power MOSFET reduces the gate coverage of the drain region of the device in order to decrease the device gate to drain capacitance C.sub.gd. A significant portion of the gate overlaying the drain region is eliminated by the removal of a portion of a polysilicon layer that is disposed over a substantial portion of the drain region that resides between the channel portions of the body regions of the device. The resulting open area, that is subsequently covered by an oxide layer, separates the polysilicon gate electrodes of the device. Finally, a metal layer is deposited over the entire structure to form the gate and source electrodes of the device.

Abstract: A power supply switching circuit ensures stable, timely, and accurate transition between a primary power source and a secondary power source of an integrated circuit. A comparison element of the circuit compares a first voltage signal derived from a primary voltage of the primary power source to a second voltage signal, also derived from the primary voltage but having a different rate of change than the first voltage signal, to generate a compare output signal. The first and second voltage signals are characterized as being equal to each other when the primary voltage is equal to a predetermined crossover point at which the integrated circuit device will be powered by the primary voltage.

Abstract: An integrated circuit structure and method provides for an integrated circuit device to respond to an edge transition detection (ETD) pulse in one of two ways. First, in response to the ETD pulse, the integrated circuit device exits a test mode at least temporarily every cycle of the integrated circuit device. Second, a node of the integrated circuit device is re-initialized every cycle if it is not forced by a super voltage indicative of test mode entry. Both of these responses prevent accidental entry of the integrated circuit device into the test mode. If the integrated circuit device is supposed to be in the test mode, it stays in the test mode. If, however, the integrated circuit device is not intended to be in the test mode, the ETD pulse forces the integrated circuit device out of the test mode. Subsequent entry into the test mode of the device is permitted if conditions for entry into the test mode have otherwise been met.

Abstract: A precision analog circuit ensures precision matching between two or more resistive elements. In order that the two or more resistive elements are truly matched, a first electrical value, such as V.sub.DS, of the two or more resistive elements are equal and a second electrical value, such as V.sub.GS, of the two or more resistive elements are equal so that a ratio of the first resistive element to the second resistive element is a predetermined value regardless of the voltage coefficients of the resistive elements.

Abstract: The present invention is directed to an improved deep trench structure, for use in junction devices, which addresses junction breakdown voltage instabilities of the prior art. The primary, or metallurgical, junction where avalanche breakdown occurs is moved away from the surface dielectric into the bulk silicon by adding a lightly doped layer adjacent to the deep trench. A preferred embodiment suitable for isolated structures places the doped layer adjacent to the sidewalls of the deep trench. A second preferred embodiment, suitable for non-isolated structures, places the doped layer adjacent to both the floor and the sidewalls of the trench.

Abstract: An integrated circuit structure and method provides a burn-in stress test mode that facilitates stress testing of an integrated circuit device in a burn-in oven. The integrated circuit structure and method is capable of disabling a time-out feature of an IC memory device during a stress test mode of the device in order to facilitate stress testing of the device in a burn-in oven. The integrated circuit structure provides for entry into the burn-in stress test mode when a supply voltage supplied to the integrated circuit device exceeds a predetermined voltage level and/or the temperature of the integrated circuit device exceeds a predetermined temperature level.

Abstract: A voltage regulator which has two regulation circuits and a comparator for controlling the two regulation circuits is disclosed. The input of the comparator is connected to a power supply voltage such that the output of the comparator changes states when the power supply voltage reaches a predetermined voltage of around 8 volts. The first regulation circuit is enabled to provide the Vcc from the battery voltage until the power supply voltage reaches around 8 volts which is when the comparator changes states. At that point, the first regulation is disabled and the second regulation circuit is enabled to provide the Vcc voltage from the power supply voltage. Since the power supply voltage never reaches the load dump high voltages, the second pass transistors never gets exposed to a high voltage condition. Also, the first transistor can withstand higher voltages since its base is grounded.

Abstract: Electro-static-discharge (ESD) protection circuits are supplied for inhibiting the destruction of buffers, drivers, logic and memory cells in Metal-Oxide-Semiconductor (MOS) devices such as a CMOS device including Static-Random-Access-Memory (SRAM). This is accomplished by tiering diodes adjacent the input of the chip and in certain specific areas internally of the chip (e.g. power supplies etc.) providing bidirectional diode protection from over-voltage.

Abstract: A catalytic converter of an engine, such as might be found in an automotive engine system, is capable of being quickly and electrically heated in order to reduce pollution emissions during critical cold start conditions. During cold start conditions, i.e. upon starting the engine, for a predetermined period of time the catalytic converter directly receives electrical power via a quick heating path connecting a catalyst power switch to the catalytic converter. Following the predetermined period of time after which the catalytic converter has been electrically heated, the catalyst power switch is connected to a junction block, such as a starter motor assembly, of the automotive engine system via a normal path.

Abstract: An improved transistor package with superior stability to wave soldering, having a nickel oxide barrier strip formed on the surface of the leads.