Abstract: Therefore, according to the present invention, the isolation between adjacent intra-polycrystalline silicon layer components of one or more polycrystalline silicon layers of an integrated circuit device may be enhanced by patterning and then implanting one or more such polycrystalline silicon layers with a high dose of oxygen or nitrogen, in the range of approximately 1.times.10.sup.17 /cm.sup.2 to 1.times.10.sup.19 /cm.sup.2. A post implant anneal is performed in either nitrogen or argon to form a layer of either silicon dioxide or silicon nitride having desirable planar characteristics. The anneal is performed at a temperature range of approximately 1000 to 1400 degrees Celsius.

Abstract: A biasing device for actively biasing the base of an RF device operating in quasi-linear modes. The biasing device provides a source of low-impedance current and high current capability. The biasing device includes three transistors, each having a base, collector and emitter and one low turn-on diode. The first and second transistors are connected such that changes in the base-emitter voltage of the biased RF device can be detected. The third transistor is configured in a Darlington configuration with the first transistor in order to provide (1) increased sensitivity to voltage changes detected by the second transistor and (2) additional collector voltage for the second transistor to prevent it from operating in saturation. The low turn-on diode is a compensating diode which thermally tracks and compensates for operating changes in the second transistor due to temperature.

Abstract: In a high density memory, such as a SRAM, DRAM, EPROM or EEPROM, a hierarchical bitline configuration is utilized such that a number of local bitlines are connected to a master bitline through interface circuitry which connects a local bitline to the master bitline. Local select signals, when set to the appropriate voltage level, couple a local bitline to the master bitline. In addition to reducing the local bitline capacitance that must be driven by memory cells, the hierarchical configuration may provide layout area savings as well.

Abstract: According to the present invention, a special operating mode of an integrated circuit device, such as a stress test mode, is entered while the integrated circuit device is powered up in order to avoid the large switching transients from multiple rows and columns being enabled simultaneously which would result if the stress test mode was entered after the integrated circuit device is powered up. Hence, power on reset can not be avoided by waiting until the power-on reset pulse is generated. The power on reset pulse of the integrated circuit device may be overridden or effectively disabled during a stress test mode, such that potential contention between the power-on reset pulse and the test mode signal of the integrated circuit device is eliminated. As a result, crowbar current is accordingly eliminated so that proper state initialization during a stress test mode may be accomplished.

Abstract: A high frequency, high power transistor is vertically isolated by providing a thermally conductive, electrically insulating substrate, upon which the transistor components (including collector, base, and emitter) are grown, positioned directly on the heat sink and a planar top surface formed on the transistor by the base metal contact, the emitter metal contact, and the collector metal contact. Vertical isolation improves the thermal management capabilities of the transistor. Moreover, such a vertically isolated transistor is well-adapted for lateral isolation, which solves the capacitance problems inherent in conventional devices.

Abstract: According to the present invention, defective element(s), such as a faulty local wordline, of an integrated circuit memory device may be selectively replaced with redundant element(s) in an efficient and flexible manner that does not require replacement of all elements associated with a master element of the memory device, thereby increasing the efficiency with which faulty elements of the memory device may be replaced. For a SRAM having a plurality of blocks, this is accomplished by combining defective block information as well as defective element information, such as bad row information, in the redundant global wordline control circuitry of the device. Then, the "normal" global wordline associated with a faulty local wordline is selectively disabled and a redundant global wordline is selectively enabled, upon detection of the address of the faulty local wordline. The normal global wordline can be enabled when the address corresponds to a non-faulty local wordline.

Abstract: A thin film transistor structure having a first and a second polycrystalline silicon layer of different conductivity types (P and N) has a high resistance contact at the resultant P-N junction. This contact resistance is reduced by forming TiSi.sub.2 (titanium disilicide) or other refractory metal silicides such as cobalt or molybdenum in specific regions, namely the P-N junction contact. Titanium disilicide consumes the portion of the second polycrystalline silicon layer in the P-N contact junction and at the same time consumes a small portion of the underlying first polycrystalline silicon layer, such that the high resistance P-N junction now no longer exists.

Abstract: According to the present invention, integrated circuitry provides for the ability to selectively introduce delays into the timing of the integrated circuit, without the expense and time associated with methods used in the prior art. As a minimum, a fuse element having at least one fuse and a transistor element having at least one transistor are placed in parallel to each other between a voltage supply of a gate of the integrated circuit and a corresponding voltage supply of the integrated circuit. When the fuse element is intact, the fuse element provides a relatively low resistance path from the voltage supply of the gate and the corresponding voltage supply of the integrated circuit. However, upon blowing the fuse element, this low resistance path is no longer available. An increased resistance path through the transistor element must be used, and the integrated circuit is slowed down accordingly.

Abstract: Internal to the transistor, an additional, direct connection is made from the internal collector to the external collector of the transistor by a fixed shunt inductance. The external power supply V.sub.s is applied to the transistor collector through an adjustable external shunt element. The adjustable external shunt element allows the user to finetune the impedance matching circuit such that the transformation ratio of the output matching circuitry is minimized.

Abstract: According to the present invention, a power amplifier with a plurality of power transistors has detection circuitry corresponding to each power transistor which detects the output power of the power transistors and allows this output power to be monitored and modified if desired. The detection circuitry generates a voltage output signal indicative of the rise and fall times achieved by the power transistor. The voltage output signal of the detection circuitry may be monitored by connecting the voltage output signal to a measuring device, such as an oscilloscope of built-in-test-equipment (BITE). Additionally, the voltage output signal of the detection circuitry may be modified by tuning input matching circuitry and/or output matching circuitry accordingly.

Abstract: According to the present invention, using an emitter-P.sup.+ (E-P) mask, a low resistance, high conductivity P.sup.+ region of a self-aligned bipolar transistor device is formed prior to the formation of a base region. The P.sup.+ diffusion and drive can thus be accomplished without concern for adverse effects on the base region of the bipolar transistor device, which is yet to be formed. After the P+ diffusion and drive step, the emitter of the bipolar transistor device is uncovered and a base mask used to allow a base implant step. A high base implant energy of approximately 35 to 40 KEV is used to completely penetrate the E-P mask layers, thereby providing a usable, linked base region in the active areas of the bipolar transistor device.

Abstract: A magnitude comparator is modified to compare the magnitudes of two large binary values more quickly and with minimum gate delays. Bit comparators are divided into groups which generate compare output signals in parallel to one another, thereby reducing magnitude comparator delay. These compare output signals are fed into a control element which determines which compare output signal is allowed to pass through as the final compare output signal. This circuitry, along with logic circuitry which indicates whether corresponding bit values within associated groups exactly match, defines a magnitude comparator block. Multiple magnitude blocks are used to facilitate the comparison of larger binary values. Each magnitude comparator block generates a compare output signal which, in turn, is an input to a corresponding gating element. Each gating element possesses a logic input signal, derived in part from its magnitude comparator block's match logic circuitry.

Abstract: Therefore, according to the present invention, borrow look ahead circuitry suitable for use in a FIFO memory allows the difference between two values to be quickly generated and this difference compared to a third value. A borrow look ahead element generates a plurality of borrow signals which are supplied to CORRESPONDING full subtractors of a subtractor section in a parallel fashion. This parallel propagation reduces gates delays between the subtractors, resulting in faster operation. Thus, the time required to supply the difference to a comparator is minimized. Adding additional levels to the borrow look ahead element further increases the speed of the borrow look ahead circuitry.

Abstract: Difference flag logic suitable for use in a FIFO memory is modified to quickly generate FIFO flag status through the use of programmable, resettable counters which eliminate the need for subtractor circuitry. A comparator is used to compare a value from a read counter with a value from a write counter. The subtractor function is replaced by offsetting the read count from the write count by a value equal to the desired FIFO flag value. Offset of the read count from the write count is accomplished by utilizing counters which provide programmable resettability. Use of programmable, resettable counters allows FIFO flag values to be chosen and implemented very easily. For instance, it is possible for a user to change from an almost full FIFO flag to a half full FIFO flag without changing any hardware at all. The counters are simply programmed and reset accordingly.

Abstract: According to the present invention, a static random access memory (SRAM) cell which is normally supplied with a nominal supply voltage under normal operating conditions, may be supplied with a super supply voltage so that tests requiring high voltages and increased current levels, such as diagnostic and reliability "stress" tests may be performed. The super supply voltage is greater in magnitude than the nominal supply voltage, and may range from approximately 7 volts to 13 volts for SRAM cells requiring a positive voltage supply. The super supply voltage level may be controlled by a test mode or by a bond pad using existing power supply circuitry.

Abstract: According to the present invention, a removable base structure, which can be a partial denture framework of the type commonly used in the art, has a curved portion that fits along the inner surfaces of either the mandibular or the maxillary teeth, and two head portions that attach to one of the two ends of the curved portion and secure the base structure to either the mandibular or the maxillary teeth. A disposable cushion portion has two cushions that cover the occlusal surfaces of select mandibular or maxillary teeth and are secured to one of the two head portions by a male/female friction retention arrangement.

Abstract: Difference flag logic suitable for use in a FIFO memory is modified to quickly generate FIFO flag status without the use of subtractor circuitry. Bit comparators, which determine if a first bit is less than, equal to, or greater than a second bit, of a magnitude comparator are divided into groups which generate compare output signals in parallel to one another, thereby reducing total magnitude comparator delay and resulting in faster operation. These compare output signals are the inputs of a control element which determines which compare output signal is allowed to pass through as the final compare output signal. The subtractor function is replaced by offsetting the read count from the write count by a value equal to the desired FIFO flag value. In addition, control of selected bits, such as the most significant bits (MSBs), of the numbers is included and may be used as necessary to avoid a wrap-around condition.

Abstract: A biasing device for actively biasing the base of an RF device operating in quasi-linear modes. The biasing device provides a source of low-impedance current and high current capability. The biasing device includes three transistors, each having a base, collector and emitter and one low turn-on diode. The first and second transistors are connected such that changes in the base-emitter voltage of the biased RF device can be detected. The third transistor is configured in a Darlington configuration with the first transistor in order to provide (1) increased sensitivity to voltage changes detected by the second transistor and (2) additional collector voltage for the second transistor to prevent it from operating in saturation. The low turn-on diode is a compensating diode which thermally tracks and compensates for operating changes in the second transistor due to temperature.

Abstract: A magnitude comparator suitable for use in a FIFO memory is modified to compare the magnitudes of two values more quickly. Bit comparators are divided into groups which generate compare output signals in parallel to one another, thereby reducing total magnitude comparator delay and resulting in faster operation. These compare output signals are fed into a control element which determines which compare output signal is allowed to pass through as the final compare output signal.

Abstract: Two addresses of an integrated circuit are selected to define a portion of the die which is functional and the portion of the die which will not be used. An input structure for addresses, which may be added to part of the electrostatic discharge (ESD) input structure of a pin, allows an address signal to be set to a predetermined logic level and to not be bonded out to the package. Additionally, another input structure allows the mapping of a signal pin to be changed. The function of a pin may need to be changed to accommodate a pinout for a different density device. This is useful when a die is put into a smaller density device package which has a pin out that does not accommodate the die. In this way, partially functional die that previously were discarded may be utilized, thereby recouping potential losses during manufacturing.