Abstract: An SOI CMOS inverter circuit in which a silicide layer in combination with body tie regions tie a p-type body region and an n-type body region together. At the same time, however, the body regions remain floating electrically so that the benefits of SOI are maintained. The silicide layer permits excess carriers to be recombined via the respective body regions so that the body region potential does not get modulated by generation/recombination effects. Thus, a hysteresis effect in the inverter circuit will be reduced.
Type:
Grant
Filed:
October 31, 2002
Date of Patent:
October 7, 2003
Assignee:
Advanced Micro Devices, Inc.
Inventors:
Srinath Krishnan, Jerry G. Fossum, Meng-Hsueh Chiang