Abstract: A semiconductor component having a metallization system that includes a multi-metal seed layer and a method for manufacturing the semiconductor component. A layer of dielectric material is formed over a lower level interconnect. A hardmask is formed over the dielectric layer and an opening is etched through the hardmask into the dielectric layer. The opening is lined with a thin conformal barrier material. A plurality of metal oxide layers are formed over the conformal barrier material. The plurality of metal oxide layers are reduced by heat treatment to form a multi-metal seed layer. An electrically conductive material is formed over the multi-metal seed layer.

Abstract: A semiconductor component having a lid for protecting a semiconductor chip and a method for manufacturing the semiconductor component. The semiconductor chip has an active surface and a mounting surface. It is flip-chip mounted to a support substrate so the active surface is adjacent the support substrate. A passive or active circuit element may be mounted to the support substrate. The mounting surface of the semiconductor chip has a radius of curvature. A thermal interface material is dispensed on the mounting surface of the semiconductor chip. A lid is coupled to the support substrate via a lid adhesive. A portion of the lid has a radius of curvature that corresponds to the radius of curvature of the semiconductor chip. A force is applied to the lid so that it contacts the thermal interface material and urges the interface material to the sides of the semiconductor chip. The force causes wetting of the thermal interface material.

Abstract: An SOI semiconductor component having a portion of a circuit element in the handle wafer and a method for manufacturing the SOI semiconductor component. An SOI substrate has a handle wafer bonded to an active wafer via a dielectric material. A shallow trench isolation structure is formed from the active wafer. A plate or electrode of a capacitor is manufactured in the handle wafer. The other plate or electrode of the capacitor is formed through the shallow trench isolation structure. A circuit element is manufactured in the active wafer such that the manufacturing steps for forming the capacitor and those for forming the circuit element may be decoupled from each other.

Abstract: An insulated gate semiconductor device (100) having reduced gate resistance and a method for manufacturing the semiconductor device (100). A gate structure (112) is formed on a major surface (104) of a semiconductor substrate (102). Successive nitride spacers (118, 128) are formed adjacent the sidewalls of the gate structure (112). The nitride spacers (118, 128) are etched and recessed using a single etch to expose the upper portions (115A, 117A) of the gate structure (112). Source (132) and drain (134) regions are formed in the semiconductor substrate (102). Silicide regions (140, 142, 144) are formed on the top surface (109) and the exposed upper portions (115A, 117A) of the gate structure (112) and the source region (132) and the drain region (134). Electrodes (150, 152, 154) are formed in contact with the silicide (140, 142, 144) of the respective gate structure (112), source region (132), and the drain region (134).

Abstract: A method for manufacturing the memory device by plasma decomposition of sulfur dioxide. A first copper electrode having a surface is provided. The surface of the first copper electrode may be made amorphous. A copper sulfide layer, CuxS, where 1?x?2, is disposed on the copper surface by decomposing sulfur dioxide in an ambient containing excess hydrogen. The copper sulfide layer may be is cuprous sulfide or cupric sulfide. A second copper electrode is coupled to the copper sulfide layer.

Abstract: A strained semiconductor device suitable for use in an integrated circuit and a method for manufacturing the strained semiconductor device. A mesa isolation structure is formed from a semiconductor-on-insulator substrate. A gate structure is formed on the mesa isolation structure. The gate structure includes a gate disposed on a gate dielectric material and has two sets of opposing sidewalls. Semiconductor material is selectively grown on portions of the mesa isolation structure adjacent a first set of opposing sidewalls of the gate structure and then doped. The doped semiconductor material is silicided and protected by a dielectric material. The gate is silicided wherein the silicide wraps around a second set of opposing sidewalls and stresses a channel region of the semiconductor device.

Abstract: An insulated gate field effect semiconductor component having a source-side halo region and a method for manufacturing the semiconductor component. A gate structure is formed on a semiconductor substrate. The source-side halo region is formed in the semiconductor substrate. After formation of the source-side halo region, spacers are formed adjacent opposing sides of the gate structure. A source extension region and a drain extension region are formed in the semiconductor substrate using an angled implant. The source extension region extends under the gate structure, whereas the drain extension may extend under the gate structure or be laterally spaced apart from the gate structure. A source region and a drain region are formed in the semiconductor substrate.

Abstract: An insulated gate semiconductor device (100) having reduced gate resistance and a method for manufacturing the semiconductor device (100). A gate structure (112) is formed on a major surface (104) of a semiconductor substrate (102). Successive nitride spacers (118, 128) are formed adjacent the sidewalls of the gate structure (112). The nitride spacers (118, 128) are etched and recessed using a single etch to expose the upper portions (115A, 117A) of the gate structure (112). Source (132) and drain (134) regions are formed in the semiconductor substrate (102). Silicide regions (140, 142, 144) are formed on the top surface (109) and the exposed upper portions (115A, 117A) of the gate structure (112) and the source region (132) and the drain region (134). Electrodes (150, 152, 154) are formed in contact with the silicide (140, 142, 144) of the respective gate structure (112), source region (132), and the drain region (134).

Abstract: A semiconductor component having an optical interconnect formed thereover and a method for manufacturing the semiconductor component. The semiconductor component has a transistor coupled to a light emitting device and another transistor coupled to a light detecting device by a metallization system. The light emitting device is optically coupled to the light detecting device by an optical interconnect formed over the transistors and the metallization system.

Abstract: An apparatus and a method for determining a vibrational characteristic of a golf club shaft. The apparatus includes a table having a clamping structure for clamping the golf club shaft thereto. A multi-dimensional accelerometer is coupled to a tip end of the golf club shaft. The multi-dimensional accelerometer is also coupled to a computer. When the golf club shaft is vibrated, the multi-dimensional accelerometer converts the vibrational signal into an electrical signal which is transmitted to the computer. The computer conditions the electrical signal and outputs a signal indicative of the frequency of vibration of the golf club shaft. The stiffness of the golf club shaft is determined from the vibrational frequency of the golf club shaft.