Abstract: A process (100) for forming a metal interconnect (102) in a semiconductor device (82) using a photoresist layer (20) having a thickness (T) of no more than 0.66 microns without forming a notch in the side (30) of the interconnect. A reactive ion etching process (118) used to remove portions of a metal layer (16) to form the interconnect includes a burst etch step (108) wherein a first high flow rate (48) of passivation gas is delivered, followed by a main metal etch step (110) wherein the flow rate of passivation gas is reduced to a second lower value.
Type:
Grant
Filed:
November 15, 2000
Date of Patent:
May 6, 2003
Assignee:
Agere Systems, Inc.
Inventors:
Stephen Ward Downey, Allen Yen, Thomas Michael Wolf, Paul B. Murphey