Abstract: Disclosed is a bipolar-CMOS circuit which includes a NMOS transistor site (18) electrically isolated from a bipolar transistor site (16). The NMOS transistor site (18) includes a semiconductor region (24) isolated from a bipolar transistor well (26) by deep diffusion ring (32). A buried layer (13) forms a bottom of the deep diffusion isolation ring (32). A backgate voltage can be applied to the isolated semiconductor region (24) of the NMOS device, which bias may be different than that applied to the substrate (10). Optimum performance of the NMOS transistor is thus assured irrespective of the magnitude of operating voltage of the bipolar transistor.

Abstract: A shell having symmetrical top and bottom parts form a chamber containing a substrate carrying package semiconductor devices and a connector. A cover fits in a hollow of the top part normally for its top surface to rest flush with the top surface of the top part. The packaged semiconductor devices on the substrate extend through apertures in the top part with the top surfaces of the packaged semiconductor devices resting substantially flush with the top surface of the top part. The cover flexes over the packaged semiconductor devices at those locations. Gripping means occur in the ends of the shell opposite the connector to aid removal of the memory card from a desired port and an interior wall and side pockets provide stress relief for removal and insertion of the connector in the desired port.