Abstract: A logic circuit for implementing a flip-flop circuit that operates stably and at high speed at a low supply voltage of about 1 V. The logic circuit includes transistors 25,26,31 for forming a first current mirror circuit 2; transistors 27,28 for converting clock signals to current signals; transistors 19,22,23 for forming a second current mirror circuit 3; and transistors 20,21,24 forming a third current mirror circuit 4. These current mirror circuits supply a current nearly equal to the current from transistors 27,28 to the circuits connected respectively to those current mirror circuits. Transistors 29,30, current source 47, voltage source 50 and voltage comparison circuit 51 form a voltage maintenance circuit. Transistors 11,12 and resistors 41,42 form an input stage of a master D flip-flop D-FF, and transistors 13,14 form the signal-holding row of the master D flip-flop D-FF.

Abstract: A system of interface circuits (15, 20-1 through 20-N) includes a mode sensing circuit (15) and one or more output circuits (20-1 through 20-N). The mode sensing circuit is arranged for producing control signals (on leads 22, 24) in response to an input signal (on lead 21). The output circuit (34-1) is arranged for producing an output data signal (DQ-1) dependent upon an input data signal (DATA) when the input signal (on lead 21) is in a first state and dependent upon the input data signal and the configuration of the connected output circuit (34-1) when the input signal is in a second state.

Abstract: In an address transition detection summing circuit, the varying address signal pulse widths can result in output signals from the address transition detection summing circuit which can compromise the performance of the associated memory circuitry. A parallel signal delay path, activated by the leading edge of the address signal, is incorporated in the address transition detection summing circuit and a logic ANDing element so that not only is the signal resulting from the trailing edge of the address signal applied to the logic ANDing element, but the trailing edge signal from the parallel signal delay path must be applied to the logic ANDing element before the trailing edge of the output pulse from the address transition detection summing circuit is generated. In the manner, an address transition always results in an output signal pulse having a preselected minimum width.

Abstract: A hybrid leadframe-over-chip (LOC) semiconductor package is generally comprised of bonding finger elements located over a surface of a semiconductor component and electrically coupled, by means of conducting wires, to the bonding pads located on the surface. In addition, at least one bonding finger is located outside the boundary of the surface of the semiconductor component. Each bonding finger located outside the boundary is coupled, by a conducting wire, to a bonding pad positioned within the boundary of the semiconductor component. In this manner, for a given semiconductor component size and for given routing and lead dimension constraints, a larger number of conducting paths can be provided between the leadframe and the semiconductor component.

Abstract: The present invention provides a modular electronic component (10) wherein a sequence: of leads (26) of a lead frame (12) differs from a sequence of bonding pads (16) on an integrated circuit (14). When lead frame (12) is placed adjacent integrated circuit (14), first and second power buses (22) and (24) are disposed on a first side (18) of bonding pads (16). First portion (30) of leads (26) and lead finger (28) are disposed on second side (20) of bonding pads (16). Bonding members (42) couple appropriate bonding pads (16) with corresponding leads (26), first and second power buses (22) and (24), and lead finger (28). In this manner, the pin out of modular electronic component (10) may be altered by incorporating appropriate lead fingers (28) without changing the sequence of bonding pads (16).

Abstract: An address transition detector stores a first output signal on an output terminal for a first predetermined period of time in response to an initial edge of an internal address signal pulse. The address transition detector stores a second output signal on the output terminal for a second predetermined period of time in response to the trailing edge of the internal address signal pulse. When the trailing edge of the internal address signal pulse is delayed from the leading edge of the internal address signal pulse by an amount greater than the first predetermined period, then output signal consists of two pulses. When the trailing edge of the internal address signal pulse is delayed from the leading edge by a time less than the first predetermined period, then the signal on the output terminal is a single expanded signal. Typically, the first and second predetermined periods are equal.

Abstract: A graphics display system includes a random access memory arranged with a split serial register and a multiplexer for coupling column of storage cells from the memory array to storage elements of the split serial register. Data stored in either a low half or a high half of the addresses of the memory array may be selectively coupled through the multiplexer to either a low half or a high half of the split serial register. For a tile oriented graphics display operation, this arrangement increases the number of choices of where within the random access memory array to store specific bits of the tile data to be displayed. Data representing a tile can be mapped into a single row of the random access memory array.

Abstract: A process is disclosed herein for increasing yield in a semiconductor circuity having redundant circuitry for replacing defective normal circuitry in the semiconductor integrated circuit. In the first step, an insufficient sinter operation (50) is carried out in a hydrogen atmosphere at a temperature of less than 350.degree. C. At this temperature, no significant change will be seen in the interface trap density. Thereafter, the integrated circuit is tested (54,56) and the defective normal circuitry then is replaced (58) with the redundant circuitry. The integrated circuit is then subjected to a sufficient sinter operation (64) which is an operation wherein the substrate is disposed at a temperature between 350.degree. C.-500.degree. C. for more than 30 minutes. This sufficient sinter operation is performed in a hydrogen atmosphere, allowing dangling bonds at the interface to be terminated with hydrogen. Preferable, the optimal temperature for the sufficient sinter is approximately 400.degree. C.

Abstract: A dynamic random access memory part 30 provides a write per bit feature by locating the respective write mask information latches 118 adjacent the respective local I/O buffers 116. The write mask information thus passes through the data latch 108 and across the data path to the local I/O buffer 116 before being latched. This reduces the area otherwise needed for the additional write mask lead, which in a x8, x16, x32 or x64 bit part can be intolerably large.

Abstract: An integrated circuit interconnect structure is provided, along with a method of forming the integrated circuit interconnect structure. A semiconductor material layer has an elongate trench formed therein. A conducting region is disposed in the trench. An insulator region overlies the conducting region. One or more contact regions are disposed through the insulator region to contact the conducting region.

Abstract: The plate voltage for a Dynamic Random Access Memory storage cell array is provided by two amplifiers. The first amplifier operates at a relatively low power level and compensates for leakage in the storage cell array, the compensation initiated by a departure of the plate from a nominal value which exceeds a preselected amount. The second amplifier operates at a higher power level and provides compensation for transients in the plate voltage resulting from the charging and discharging of the storage cells. Because the transients occur when the storage cells are accessed, the second amplifier is enabled only when a group of storage cells is accessed. In addition to operating at a higher power level, the second amplifier is more sensitive and responds to smaller excursions from the nominal voltage. Both the first and the second amplifiers have separate driver circuits for responding to excursions above and for responding to excursions below the nominal voltage.

Abstract: MESFET devices are fabricated on a semiconductor substrate using a LOCOS (localized oxidation of silicon) process twice during the fabrication. The first LOCOS process provides device separation with a self-aligned thick-field oxide (SATO). The second LOCOS provides separation of gate and source/drain regions for each device, and self-aligns the gate contact with the channel implant. Devices fabricated by this method exhibit reduced series resistance, and improved metal step coverage.

Abstract: Non-volatile JRAM cell having interelectrode non-volatile capacitance which is readable and varies with the electrical charge on elements of the device. To program the nonvolatile capacitance, the address lines (word line and bit line) are biased so that a charge is given to the nonvolatile multidielectric stack between the MIS gate and the JFET source of the cell. For a charge of one polarity, an inversion layer of electrons (for a P-type substrate) is formed on the surface of the JFET source, increasing the capacitance between the MIS gate electrode and the JFET gate electrode. For the opposite polarity, an accumulation layer forms at the JFET source surface, decreasing the interelectrode capacitance. The cell is read by presetting one address line, floating that line, then putting a pulse on the other line while reading the voltage output on the floating line.

Abstract: An apparatus having a reservoir for enclosing a fluid and a valve for selectively applying gas under pressure to said reservoir and venting said reservoir to the ambient air. A controller supplies a pulse of predetermined duration selected from a plurality of durations to actuate the valve to apply the gas under pressure to the reservoir for expelling a predetermined amount of ink therefrom through a tube by compensation for dynamic effects. The ink is transferred from one end of the tube to a selected item of a sheet of items by moving the end of the tube closely adjacent to the sheet while the ink is being expelled from the reservoir and through the tube for transfer to the individual item.

Abstract: An apparatus and method of forming aluminum balls utilized for ball bonding. The aluminum balls are formed in a moist argon atmosphere by applying an electrical potential across a spark gap causing a spark to occur which causes the end of the aluminum wire to melt, forming an aluminum ball.

Abstract: A method for the fabrication of a cured polyamic acid film having apertures therein selectively etched to provide sidewalls sloped at a controlled angle. Such films are used in the fabrication of integrated circuits having two or more levels of metallization, to provide electrical insulation between metal levels. The apertures therein are required to have sloped sidewalls in order to enhance the yields of circuits having reliable contact between metal levels.

Abstract: An improvement in a communication system is disclosed having a transmitter which transmits a pulse width modulated control signal having a synchronizing pulse, a reference pulse, and at least one control function pulse encoded therein. At least one receiver receives the transmitted control signal and detects the pulses encoded therein. In response to each detected pulse, a timing circuit in each receiver provides a timing pulse having a width related to a reference signal. A reference controller compares the width of the detected reference pulse to the width of the timing pulse and provides a reference calibration signal at a level automatically selected to reduce the compared pulse width difference. A function controller may be provided to compare the width of the detected control function pulse to the width of the timing pulse, and to perform a control function in response to a predetermined compared width difference therebetween.

Abstract: This invention deals with the fabrication of radiation emitting diodes having a small diameter shaped integral microlens formed by etching. Initially an oxide layer is deposited on the backside of the processed slice; then a ring pattern is opened in the oxide. An etch is used to form a ring groove with a mesa in the center. The center oxide dot over the mesa is removed and the etching continued to round off the edges of the mesa and to form a smooth shaped structure. Various shapes and diameters may be achieved with different ring dimensions and with different etch times.