Abstract: A method for producing a thin panel liquid crystal display system (20) for producing images comprising providing a mother glass (32) having at least two active glass substrates (34) therein, adhering the mother glass (32) to a handle substrate (38) to provide strength and rigidity to the mother glass (32), printing said active glass substrates (34) with grid lines, cutting the mother glass (32) between the active glass substrates (34), separating the active glass substrates (34) from one another, placing two active glass substrates (34) in parallel with one another, disbursing a plurality of glass beads on one of the active glass substrates (34), injecting liquid crystal display material between the active glass substrates (34), sealing the active glass substrates (34) together, and separating each of the active glass substrates (34) from the handle substrate (38).

Abstract: An improved portable notebook computer having a base (15) connected to a display unit (20) that folds along a spine (26). The display unit (20) is pivotally coupled to the base (15) for motion and houses a plurality of display components including a light source (85), light guide (80) and LCD (50). The display drive circuits (115), light source (85), power board (165) and related display components are relocated to the base (15) reducing the thickness and weight of the display unit (20). PWB's (115, 120, 125) used to control LCD (50) display functions are maintained on the display case back (70) to take advantage of available space within the display unit (20). A flexible circuit (330) extends from the base (15) to the display unit (20) to connect the display drive circuits (115) to the PCB's (115, 120, 125) for controlling LCD (50) display functions.

Abstract: Generally, according to the present invention, the sidewall of the adhesion layer (e.g. TiN 36) in a lower electrode is pre-oxidized after deposition of an unreactive noble metal layer (e.g. Pt 38) but before deposition of an HDC material (e.g. BST 42). An important aspect of the present invention is that the pre-oxidation of the sidewall generally causes a substantial amount of the potential sidewall expansion (and consequent noble metal layer deformation) to occur before deposition of the HDC material. One embodiment of the present invention is a microelectronic structure comprising a supporting layer having a principal surface, and an adhesion layer overlying the principal surface of the supporting layer, wherein the adhesion layer comprises a top surface and an expanded, oxidized sidewall (e.g. TiO.sub.2 40).

Abstract: A method for designing and operating a multi-processor computer system, in which data required for performing a task is determined by a first processor and then downloaded to a second processor that will execute the task. The data is associated with regions whose uses are expected by the second processor but whose actual contents are determined by the first processor. The method accommodates mutually exclusive access by both processors to memory of the second processor, while providing all data required for the task in a single read operation.

Abstract: An integrated liquid crystal display and backlight system for generating video images for a portable computer (12) comprising a top glass (32), a bottom glass (34) and a thin film transistor and liquid crystal layer (36) disposed therebetween, a diffuser (38) bonded to the bottom glass (34) on the side opposite the top glass (32), a substrate (40) bonded to the diffuser (38) opposite the bottom glass (34) having an array of semispherical cavities (42) each having an aluminized surface (44), a phosphor layer (46) coating the aluminized surfaces (44), an array of indium tin oxide conductors (48) electrically connected to the aluminized surfaces (44) and disposed within the cavities (42), and a volume of mercury gas (50) filling the cavities (42) such that when a voltage (54) is established between the aluminized surfaces (44) and the indium tin oxide conductors (48), the phosphor (46) becomes excited and produces backlight for the liquid crystal display system (26).

Abstract: A network (10) of mobile computing devices (18) communicates by receiving and rebroadcasting messages using wireless transmission. A message is initiated by first mobile computing device and transmitted to a set of other mobile computing devices which may be selected on an ad hoc basis. The receiving mobile computing devices rebroadcast the message to other of the mobile computing devices (18) which have not received the message. The message is repeatedly rebroadcast until all mobile computing devices (18) have received the message or, if the message is intended for particular selected mobile computing devices (18), until all selected devices have received the message.

Abstract: A transparent telephone access system using voice authorization includes a method and system (30 and 60) to protect against the unauthorized use of telephone network (20). By receiving a spoken telephone number (14) from telephone unit (16) and recognizing the spoken phrase that corresponds to telephone number (24), the method and system permit transmission through telephone network (20) to telephone (22). The method and system record spoken phrase (14) in voice recognition server system (18). For the spoken phrase, a voice-template is formed and compared with a voice template formed from a composed phrase including pre-existing or stored spoken digits. In response to the comparison, use of telephone system (16) through telephone network (20) is permitted.

Abstract: Portable electronic devices, such as notebook computers, are provided with the capability of a low profile and light weight keyboard, allowing greater reduction in the size and weight of portable computers without compromising the functionality. In specific embodiments, the present invention provides laptops, notebooks, and sub-notebooks with a low profile keyboard having a polymer top surface. In an embodiment of the invention, a structural rib 214 surrounds at least some portion of the key to advantageously provide a firm offset of the key top from the circuit board 206 for increased key travel over prior art designs. In another embodiment of the present invention, the keyboard key includes alignment pistons 218 affixed to the flexible key layer 202 and extend into holes in the circuit board 206 to provide advantages such as keeping the key's top surface flat, preventing the key from tilting or collapsing on only one or two sides.

Abstract: An apparatus and method for converting a subtractive device decode cycle to a peripheral component interface device decode cycle comprising a data communications bus (45), an interface (110) to the data communications bus (45), a function decoder (125) and device decoder (12) coupled to the interface (110). The function decoder (125) and device decoder (120) detect the presence of predetermined command and device types, respectively, on the data communications bus (45). The function decoder (125) and device decoder (120) feed a device select drive circuit (135) when the proper address and command types are detected. Device addresses in preselected ranges are pass-through and maintained internally in order to prevent the subtractive decode agent (90) from grabbing the bus cycle. Also, a positive decode cycle detection circuit (130) is operably coupled to the device select drive circuit (135) to detect the presence of positive decode cycles after the subtractive decode device select signal has been asserted.

Abstract: The present invention provides a method and a circuit architecture whereby a time delay for optical signals in an integrated optical circuit is implemented in a hybrid configuration. For example, a hybrid time delay circuit could be implemented with a three chip set composed of a switch chip 34 placed between two delay chips 36,38. The delay chips may include one or more delay loops 44 and preferably an associated bypass loop for each delay loop 42. The switch chip contains an optical switch 20 for each delay loop on the delay chips and may contain switch control circuitry or an interface to external switch control circuitry.

Abstract: A sensor 20 is formed on semiconductor substrate 22. Dielectric layers 23 and 24 are formed on the face and backside of substrate 22, respectively. Metal leads 26 and 28 contact the substrate through openings in the dielectric layer 23. The leads 26 and 28 are also connected to the set of interleaved longitudinal contact fingers 27 and 29. Additionally, a pair of backside contacts 30 and 32 are formed on the dielectric layer 24. The backside contact 30 is in contact only with the metal lead 26 through a conductive region 34.

Abstract: A method of identifying an object and determining in which of at least two areas the object is located is disclosed. The method includes the steps of: focusing a first directional antenna (18) on a first area (28a), focusing a second directional antenna on a second area (28b), transmitting a first field strength pulse (44) from said first directional antenna (18), transmitting a second field strength pulse (46) from said second directional antenna (18), and comparing in a transponder (14) the first field strength pulse (44) to the second field strength pulse (46) to determine in which of the two areas (28a,28b) the transponder (14) is located. Other devices, systems and methods are also disclosed.

Abstract: A composite dieletric film for final passivation of an integrated circuit. First, plasma-enhanced TEOS oxide is deposited to a thickness of 2000 .ANG., followed by thermal O.sub.3 -TEOS oxide to a thickness of 8000 .ANG., and then silicon nitride to a thickness of 10,000 .ANG..

Abstract: A lead (10) for a semiconductor device (12) comprising a strip portion (14) comprising a first substantially horizontal portion (18) connected to the semiconductor device (12), a substantially vertical portion (20) connected to the first substantially horizontal portion (18), and a second substantially horizontal portion (22) connected to the substantially vertical portion (20) with at least one hole (16) disposed in the strip portion (14). A method of providing an electrical contact for connecting a semiconductor device (12) to a surface (24) comprising the steps of extending at least one lead (10) from the semiconductor device (12) and slotting the lead (10).

Abstract: In accordance with the present invention, there is provided a method by which narrow lateral dimensioned microelectronic structures can be formed using low temperature processes. An uncured resist layer (e.g. PMMA 42) is deposited on a supporting layer (e.g. silicon 40) and patterned. Then, by using an isotropic process such as a low temperature chemical vapor deposition, a conformal layer (e.g. silicon oxynitride 44) is deposited substantially evenly on the vertical walls and on the horizontal surfaces of the uncured resist layer. An anisotropic etch such as reactive ion etching is then used to substantially remove the conformal layer from the horizontal surfaces without substantially etching the conformal layer from the vertical walls of the resist. The resist can then be selectively removed, producing isolated vertical sidewall structures (e.g. silicon oxynitride 46) which could be used, for example, as a negative tone mask. Alternatively, instead of removing the resist, another resist layer (e.g.

Abstract: A fuse for a semiconductor integrated circuit is provided wherein a strip of corrosive material (82), such as aluminum, has one end thereof connected to a conductive strip (84) of a non-corrosive material and the other end thereof connected to a strip (94) of non-corrosive conductive material. The one end of the conductive strip (82) connected to the conductive strip (84) is connected through a contact (88). Similarly, the other end of the strip (82) is connected through a contact (96) to the non-corrosive conductive strip (94). The strips 84 and 94 provide a barrier to corrosion. This occurs whenever a break (104) is formed in the fuse to expose the ends of the fuse (82) at the break to a corrosive atmosphere. Alternatively, the fuse could be connected to corrosive underlying layers with contacts (118) and (124) of non-corrosive material such as a polysilicon or a polyside, or the active region of the substrate itself.

Abstract: A lid alignment assembly for components such as semiconductor device packages, includes a boat 40 for holding at least one semiconductor package 36 and an alignment cover 10 mountable to the boat 40 and having at least one opening 11a therein for positioning a lid 11 over the semiconductor package 36 received in the boat 40. A plurality of tapered tabs 12-19 extend from the cover 10 and contact one or both of the boat 40 and semiconductor package 36 to direct the semiconductor package 36 to a predetermined position beneath the cover 10 and said at least one cover opening 11a.

Abstract: A method of forming a planar dielectric layer over an interconnect pattern which requires fewer processing steps and has a lower dielectric constant than is obtained in the prior art. The method comprises providing a substrate having an electrical interconnect pattern thereon, forming a first layer of dielectric over the interconnect pattern, preferably by plasma generated TEOS oxide, forming a porous second layer of silicon-containing dielectric with low dielectric constant different from the first layer over the first dielectric layer from an inorganic silicon-containing composition, preferably hydrogen silsesquioxane and forming a third layer of dielectric different from the second layer over the second dielectric layer, preferably by a plasma generated TEOS oxide.

Abstract: A semiconductor memory device (20) includes N bitlines (31, 32, 33, 34) addressable by a partially decoded column address, wherein N is greater two. A column address selection lead (YSEL) has plural segments, each of which overlays a length of one of the bitlines. Each segment of the column address selection lead overlays no more than approximately 1/N of the length of a bitline. Adjacent column address selection leads are separated by approximately the pitch of N-1 bitlines.

Abstract: A redundancy passgate circuit is implemented in NMOS technology in order to provide a more rapid transmission of the transmitted signals. The circuit provides for the more rapid signal transmission by reducing the capacitance experienced by the input signals. The reduced capacitance loading is achieved at the expense of a greater layout area and a requirement for an on-chip power supply.