Abstract: A method and system for managing a cache including a plurality of entries are described. According to the method, first and second cache operation requests are received. In response to receipt of the second cache operation request, an entry among the plurality of entries is identified for replacement. In response to a conflict between the first and the second cache operation requests, an entry among the plurality of entries other than the identified entry is replaced. In one embodiment, the alternative entry is replaced if the first cache operation request specifies the entry identified for replacement in response to the second cache operation request.

Abstract: A computer network includes a plurality of clients coupled to a server. The server includes data storage that stores network administration software and a shared client operating system. In response to detection of a new client attached to the computer network that has not previously been attached, the network administration software boots the shared client operating system on the new client. In one embodiment, the network administration software boots the shared client operating system on the new client in response to obtaining user logon information, where the user logon information is the only user input required for the network administration software to boot the shared client operating system on the new client.

Abstract: A method of storing values in a cache used by a processor of a computer system, the cache having two or more cache directories. An address tag associated with the memory block is written into a first cache directory during an initial processor cycle, the address tag is written into a second cache directory during the next or subsequent processor cycle. Another address tag associated with a different memory block may be read from the second cache directory during the initial processor cycle. Additionally, another address tag associated with yet a different memory block may be read from the first cache directory during the subsequent processor cycle.