Abstract: Improved insulating modular panels are manufactured to incorporate into each insulating modular panel at least one vacuum insulation panel. Vacuum insulation panels are conveyed seriatim toward a pultrusion die which ultimately produces the insulating modular panels as a continuous block. Joint spacings or gaps between adjacent vacuum insulation panels and sides of the vacuum panels are filled with foam or preformed filler material to form a substantially continuous inner core which has substantially continuous side edges. Reinforcement material is applied to the inner core. The reinforcement material can be impregnated with resin prior to its application to the inner core or resin may be injected into the pultrusion die. In either event, a continuous elongated block of insulating modular panels emerges from the pultrusion die. The continuous elongated block is severed at joint spacings or gaps between adjacent vacuum insulation panels to form insulating modular panels of desired sizes from the block.

Abstract: Intermodule testing in a computer system including a plurality of modules interconnected via a system bus is performed by means of a serial test bus which is incorporated into the computer system for testing components, for example integrated circuits, used to construct the modules of the computer system. Intermodule test data is maintained in memory on each of the modules and is accessible through operations of the serial test bus. Intermodule test data is retrieved by the serial test bus and used to set up the modules so that one module drives the system bus with test signals defined by test vectors included within the intermodule test data. The remaining modules are set up to receive the test signals. Tables are developed in accordance with the intermodule test data to define which test signals drive which system bus leads and also which receiving modules receive the test signals.

Abstract: Multiple processor systems are configured to include at least two system or memory buses with at least two processors coupled to each of the system buses, and at least two I/O buses which are coupled to the system buses to provide multiple expansion slots hosting up to a corresponding number of I/O bus agents for the systems at the cost of a single system bus load for each I/O bus. Each of the system and I/O buses are independently arbitrated to define decoupled bus systems for the multiple processor systems of the present invention. Main memory for the systems is made up of at least two memory interleaves, each of which can be simultaneously accessed through the system buses. Each of the I/O buses are interfaced to the system buses by an I/O interface circuit which buffers data written to and read from the main memory or memory interleaves by I/O bus agents.

Abstract: A CMOS circuit for receiving ECL signals includes a triple-feedback arrangement for dynamically biasing a current source transistor of a differential amplifier of the CMOS circuit. The CMOS receiver circuit of the present application comprises a differential amplifier for generating an output signal representative of the difference between a reference signal and an ECL input signal and an inverter circuit for receiving the output signal and generating a CMOS compatible output signal. The differential amplifier includes a first current source transistor. A first CMOS transistor is connected to receive the ECL input signal and a second CMOS transistor is connected to receive the reference signal.

Abstract: A DC to DC converter is disclosed wherein the output voltage is regulated by the control of current pulses in an inverter stage. The converter output voltage and a defined reference voltage are compared to generate error signals and current flow in the inverter stage is monitored to generate proportional current signals. The error signals are directly compared to the current signals by a comparing circuit which comprises a voltage ampliflier and a current source. The error signals are coupled to the voltage amplifier which maintains a corresponding voltage on one side of a resistor. The current signals are coupled to the current source which is connected to the other side of the resistor and maintains the current flow through the resistor at a level equal to the current signals.

Abstract: A table translator circuit arrangement comprises a plurality of random access word organized memories, input circuitry, output circuitry, and control circuitry. The word locations of each memory are separated into control and data locations defined by corresponding ranges of memory access addresses. Each table entry comprises one or more access control bits and associated data. Each table address defines a control location in one memory of the plurality and data locations in additional memories of the plurality. An entry to be written into the table is provided to input rotate circuitry which is controlled by a portion of the table address which defines the location at which the entry is to be written. The input rotate circuitry delivers the access control bits of the entry to a memory in which a control location is accessed and delivers the associated data bits to additional memories in which data locations are accessed.