Abstract: An optical switch in which states are defined by dynamic charge storage, rather than contention resolution, and which switches using pulsed radiation having a wavelength somewhat longer than the exciton wavelength in a SEED diode. The switch does not exhibit or need bistability but switches at a relatively low energy as compared to S-SEEDS switched at the exciton wavelength.
Abstract: Defect density in a semiconductor process sequence that uses two local oxidations is reduced by using an approximately 1:1 ratio of nitride to oxide thickness in the second local oxidation step and an annealing step.
Abstract: A high transconductance field effect transistor is realized by controlling the doping level in a conducting channel buried beneath a heterointerface. In one exemplary embodiment, a channel comprising an undoped, high mobility, narrow band gap quantum well in combination with an intermediate band gap layer is formed beneath a heterointerface. The heterojunction interface is between a wide band gap layer and the quantum well region. A charge sheet having the same conductivity type as the wide bandgap layer is formed near the heterointerface. Advantageously, the transconductance is enhanced by conduction in the undoped filled quantum well region.
Abstract: In the manufacture of semiconductor integrated-circuit devices, electrical contact to semiconductor regions such as, e.g., source and drain regions of field-effect transistors typically is made by a structure in which a silicide is intermediary to silicon and metal. The invention provides for processing, after window formation and before metal deposition, which includes deposition of a silicide-forming material, and annealing in a non-oxidizing atmosphere. Preferably, the atmosphere includes a component which forms a conductive compound with the silicide-forming material. Resulting contact structures have good step coverage, low contact resistance, low interdiffusion of metal into semiconductor, and fail-safe operation in the event of breaks due to electromigration. Moreover, in the case of misalignment of a window, a contact region may be extended laterally by dopant diffusion, thereby safeguarding the junction. Tolerance to window misalignment permits increased packing density, e.g.
Abstract: An integrated circuit having one or more antifuses which connect electrical components through a dielectric layer. The antifuse is formed before the thick dielectric is deposited and patterned to form windows which expose the antifuse.
Abstract: A programmable circuit uses antifuse to program the circuit with the antifuses located not in the logic path but located so they control the voltage applied to the gate electrode of a transistor located in the logic path.
Abstract: Solder tape automated bonding of leads to an integrated circuit chip is performed using a constant temperature, flat faced thermode and a clamping plate to keep the leads in contact with the integrated circuit chip.
Abstract: A planar surface is produced in integrated circuit processing by patterning a bilevel structure of a conductor and a sacrificial layer followed by directional deposition of a dielectric and lift off of the sacrificial layer. An additional dielectric layer may now be deposited if desired.
Abstract: A single beam of radiation is split and part of the beam is directed to conductive links, e.g. runners on a substrate. Analysis of the incident beam and the beam reflected from the substrate permits a determination of when the link is blown and rendered non-conductive and when significant substrate involvement occurs.
Abstract: In the manufacture of an integrated-circuit device, periodic interruption of grain growth during chemical vapor deposition of a metal film results in enhanced surface smoothness and ease of patterning. Interruption of grain growth is by deposition of an auxiliary material which, in the interest of high conductivity of the film, may be conductive, may form a conductive compound or alloy, or may be eliminated upon additional metal deposition. When the metal is tungsten, silicon is a preferred grain-growth interrupting material.
Abstract: Integrated circuits are fabricated with thick self-aligned silicide runners on the field oxide by etching back the first dielectric to expose patterned polysilicon on the field oxide and then forming a silicide on the patterned polysilicon.
Type:
Grant
Filed:
October 12, 1989
Date of Patent:
June 19, 1990
Assignee:
AT&T Bell Laboratories
Inventors:
Steven J. Hillenius, Kuo-Hua Lee, Chih-Yuan Lu, Janmye Sung
Abstract: Overetching of gate runners, which may be silicided, during window etching is prevented by opening windows in the dielectric to expose the top of the silicide layer on the runners and then depositing a metal, such as tungsten, which has a high etch selectivity with respect to the dielectric. Etching can then continue to open windows which expose the source/drain regions without overetching of the gate runners because the etch used has high selectivity with respect to the dielectric and the metal.
Abstract: A transferred electron device is described in which the charge of the drifting packets is imaged perpendicular to the charge-packet direction so that essentially all of the packet-averaged, space-charge field is normal to the drift direction. This permits continuous formation of contiguous charge packets.
Type:
Grant
Filed:
December 28, 1984
Date of Patent:
January 16, 1990
Assignee:
American Telephone and Telegraph Company, AT&T Bell Laboratories
Inventors:
James A. Cooper, Jr., Karvel K. Thornber
Abstract: A bidirectional optical communications system is described using a multiple quantum well structure as both a photodetector and light modulator.
Type:
Grant
Filed:
February 21, 1986
Date of Patent:
November 7, 1989
Assignee:
AT&T Bell laboratories American Telephone and Telegraph Company
Abstract: A molecular beam epitaxy method of growing Ge.sub.x Si.sub.1-x films on silicon substrate is described. Semiconductor heterostructures using Ge.sub.x Si.sub.1-x layers grown on either Ge or Si substrates are described.
Type:
Grant
Filed:
May 28, 1987
Date of Patent:
August 29, 1989
Assignee:
American Telephone and Telegraph Company, AT&T Bell Laboratories
Inventors:
John C. Bean, Leonard C. Feldman, Anthony T. Fiory
Abstract: A lead frame for mounting a semiconductor chip in an integrated circuit package incorporates a deformation absorbing member as an integral part of the paddle support arm so that the initial, desired physical and electrical characteristics are unaltered after a forming operation such as paddle downsetting.
Type:
Grant
Filed:
November 24, 1986
Date of Patent:
February 7, 1989
Assignee:
American Telephone and Telegraph Co., AT&T Bell Labs
Abstract: Low temperature sintering of grade materials sintered to 99 percent of the theoretical density is described using TiO.sub.2 powder prepared by hydrolyzing titanium isopropoxide and calcining at 850.degree. C.
Type:
Grant
Filed:
April 13, 1987
Date of Patent:
January 24, 1989
Assignee:
American Telephone and Telegraph Company, AT&T Bell Laboratories
Abstract: Periodically modulating the temperature of a semiconductor laser while maintaining constant optical power permits very precise measurements of the operating parameters of the laser.
Type:
Grant
Filed:
August 14, 1987
Date of Patent:
January 10, 1989
Assignee:
American Telephone and Telegraph Company, AT&T Bell Laboratories
Abstract: An ordered-disordered transition is observed in semiconductor alloys which enables either the ordered or disordered structure to be produced.